Current sensing method and apparatus particularly useful for a memory array of cells having diode-like characteristics
First Claim
1. In a memory array having at least two memory planes of memory cells with diode-like conduction characteristics for at least one of two memory cell data states, each respective memory cell within a memory plane coupled between a respective one of a plurality of X-lines and a respective one of a plurality of Y-lines associated with the memory plane, a method of sensing the data state of one or more selected memory cells comprising the steps of:
- biasing the X-lines and Y-lines so that a forward bias voltage of at least about 1 volt is impressed across one or more selected memory cells, and further so that no appreciable bias voltage is impressed across at least a first group of half-selected memory cells; and
sensing current flow on at least one of the respective X-line or respective Y-line associated with each selected memory cell, to determine the data state of each selected memory cell;
wherein each of the first group of half-selected memory cells is coupled to a selected X-line or Y-line whose current flow is sensed; and
wherein the memory cells comprise an amorphous solid.
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Abstract
A memory array includes a sensing circuit for sensing bit line current while keeping the voltage of the selected bit line substantially unchanged. The word lines and bit lines are biased so that essentially no bias voltage is impressed across half-selected memory cells, which substantially eliminates leakage current through half-selected memory cells. The bit line current which is sensed arises largely from only the current through the selected memory cell. A noise detection line in the memory array reduces the effect of coupling from unselected word lines to the selected bit line. In a preferred embodiment, a three-dimensional memory array having a plurality of rail-stacks forming bit lines on more than one layer, includes at least one noise detection line associated with each layer of bit lines. A sensing circuit is connected to a selected bit line and to its associated noise detection line.
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Citations
42 Claims
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1. In a memory array having at least two memory planes of memory cells with diode-like conduction characteristics for at least one of two memory cell data states, each respective memory cell within a memory plane coupled between a respective one of a plurality of X-lines and a respective one of a plurality of Y-lines associated with the memory plane, a method of sensing the data state of one or more selected memory cells comprising the steps of:
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biasing the X-lines and Y-lines so that a forward bias voltage of at least about 1 volt is impressed across one or more selected memory cells, and further so that no appreciable bias voltage is impressed across at least a first group of half-selected memory cells; and sensing current flow on at least one of the respective X-line or respective Y-line associated with each selected memory cell, to determine the data state of each selected memory cell; wherein each of the first group of half-selected memory cells is coupled to a selected X-line or Y-line whose current flow is sensed; and wherein the memory cells comprise an amorphous solid. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15)
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16. In a memory array having at least two memory planes of memory cells with diode-like conduction characteristics for at least one of two memory cell data states, each respective memory cell within a memory plane coupled between a respective one of a plurality of X-lines and a respective one of a plurality of Y-lines associated with the memory plane, a method of sensing the data state of one or more selected memory cells comprising the steps of:
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biasing the X-lines and Y-lines so that a forward bias voltage of at least about 1 volt is impressed across one or more selected memory cells, and further so that no appreciable bias voltage is impressed across at least a first group of half-selected memory cells; and sensing current flow on at least one of the respective X-line or respective Y-line associated with each selected memory cell, to determine the data state of each selected memory cell; wherein each of the first group of half-selected memory cells is coupled to a selected X-line or Y-line whose current flow is sensed; and wherein the X-lines are connected to respective anode terminals of some associated memory cells, and to respective cathode terminals of other associated memory cells. - View Dependent Claims (17)
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18. An integrated circuit comprising:
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a memory array having at least two memory planes of memory cells with diode-like conduction characteristics for at least one of two memory cell data states, each respective memory cell within a memory plane coupled between a respective one of a plurality of X-lines and a respective one of a plurality of Y-lines associated with the memory plane; means for biasing the X-lines and Y-lines so that a forward bias voltage of at least about 1 volt is impressed across one or more selected memory cells, and further so that no appreciable bias voltage is impressed across at least a first group of half-selected memory cells; and means for sensing current flow on at least one of the respective X-line or respective Y-line associated with each selected memory cell, to determine the data state of each selected memory cell; wherein each of the first group of half-selected memory cells is coupled to a selected X-line or Y-line whose current flow is sensed; and wherein the memory cells comprise an amorphous solid. - View Dependent Claims (19, 20, 21, 22, 23, 24, 25, 26, 27, 28)
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29. An integrated circuit comprising:
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a memory array having at least two memory planes of memory cells with diode-like conduction characteristics for at least one of two memory cell data states, each respective memory cell within a memory plane coupled between a respective one of a plurality of X-lines and a respective one of a plurality of Y-lines associated with the memory plane; means for biasing the X-lines and Y-lines so that a forward bias voltage of at least about 1 volt is impressed across one or more selected memory cells, and further so that no appreciable bias voltage is impressed across at least a first group of half-selected memory cells; and means for sensing current flow on at least one of the respective X-line or respective Y-line associated with each selected memory cell, to determine the data state of each selected memory cell; wherein each of the first group of half-selected memory cells is coupled to a selected X-line or Y-line whose current flow is sensed; and wherein the X-lines are connected to respective anode terminals of some associated memory cells, and to respective cathode terminals of other associated memory cells. - View Dependent Claims (30)
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31. An integrated circuit comprising:
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a memory array having at least two memory planes of memory cells with diode-like conduction characteristics for at least one of two memory cell data states, each respective memory cell within a memory plane coupled between a respective one of a plurality of X-lines and a respective one of a plurality of Y-lines associated with the memory plane; means for biasing the X-lines and Y-lines so that a forward bias voltage of at least about 1 volt is impressed across one or more selected memory cells, and further so that no appreciable bias voltage is impressed across at least a first group of half-selected memory cells; and means for sensing current flow on at least one of the respective X-line or respective Y-line associated with each selected memory cell, to determine the data state of each selected memory cell; wherein each of the first group of half-selected memory cells is coupled to a selected X-line or Y-line whose current flow is sensed; and wherein the memory cells comprise an organic polymer.
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32. An integrated circuit comprising:
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a memory array having at least two memory planes of memory cells with diode-like conduction characteristics for at least one of two memory cell data states, each respective memory cell within a memory plane coupled between a respective one of a plurality of X-lines and a respective one of a plurality of Y-lines associated with the memory plane; means for biasing the X-lines and Y-lines so that a forward bias voltage of at least about 1 volt is impressed across one or more selected memory cells, and further so that no appreciable bias voltage is impressed across at least a first group of half-selected memory cells; and means for sensing current flow on at least one of the respective X-line or respective Y-line associated with each selected memory cell, to determine the data state of each selected memory cell; wherein each of the first group of half-selected memory cells is coupled to a selected X-line or Y-line whose current flow is sensed; and wherein the memory cells comprise a phase change material.
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33. In a memory array having at least two memory planes of memory cells with diode-like conduction characteristics for at least one of two memory cell data states, each respective memory cell within a memory plane coupled between a respective one of a plurality of X-lines and a respective one of a plurality of Y-lines associated with the memory plane, a method of sensing the data state of one or more selected memory cells comprising the steps of:
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biasing the X-lines and Y-lines so that a forward bias voltage of at least about 1 volt is impressed across one or more selected memory cells, and further so that no appreciable bias voltage is impressed across at least a first group of half-selected memory cells; and sensing current flow on the at least one of the respective X-line or respective Y-line associated with each selected memory cell relative to a noise current flowing in an associated noise detection line within the array, to determine the data state of each selected memory cell; wherein each of the first group of half-selected memory cells is coupled to a selected X-line or Y-line whose current flow is sensed. - View Dependent Claims (34, 35, 36)
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37. An integrated circuit comprising:
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a memory array having at least two memory planes of memory cells with diode-like conduction characteristics for at least one of two memory cell data states, each respective memory cell within a memory plane coupled between a respective one of a plurality of X-lines and a respective one of a plurality of Y-lines associated with the memory plane; means for biasing the X-lines and Y-lines so that a forward bias voltage of at least about 1 volt is impressed across one or more selected memory cells, and further so that no appreciable bias voltage is impressed across at least a first group of half-selected memory cells; and means for sensing current flow on at least one of the respective X-line or respective Y-line associated with each selected memory cell, to determine the data state of each selected memory cell; wherein each of the first group of half-selected memory cells is coupled to a selected X-line or Y-line whose current flow is sensed; and wherein the means for sensing current flow is configured to sense a current flowing outward from the memory array. - View Dependent Claims (38)
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39. An integrated circuit comprising:
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a memory array having at least two memory planes of memory cells with diode-like conduction characteristics for at least one of two memory cell data states, each respective memory cell within a memory plane coupled between a respective one of a plurality of X-lines and a respective one of a plurality of Y-lines associated with the memory plane; means for biasing the X-lines and Y-lines so that a forward bias voltage of at least about 1 volt is impressed across one or more selected memory cells, and further so that no appreciable bias voltage is impressed across at least a first group of half-selected memory cells; and means for sensing current flow on at least one of the respective X-line or respective Y-line associated with each selected memory cell relative to a noise current flowing in an associated noise detection line within the array, to determine the data state of each selected memory cell; wherein each of the first group of half-selected memory cells is coupled to a selected X-line or Y-line whose current flow is sensed. - View Dependent Claims (40, 41, 42)
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Specification