Multiple twin cell non-volatile memory array and logic block structure and method therefor
First Claim
1. A non-volatile memory cell array comprising within a first array block a first plurality of X-lines configured to be individually selected in a write mode of operation and configured to be simultaneously selected in a read mode of operation, and each associated with a first Y-line group numbering at least one Y-line and also associated with a second Y-line group numbering at least one Y-line.
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Accused Products
Abstract
Extremely dense memory cell structures provide for new array structures useful for implementing memory and logic functions. An exemplary non-volatile memory array includes a first plurality of X-lines configured to be logically identical in a read mode of operation, and each associated with a first Y-line group numbering at least one Y-line. Each of the first plurality of X-lines may also be associated with a second Y-line group numbering at least one Y-line. In some embodiments, the first and second Y-Line groups are simultaneously selectable in a read mode and, when so selected, are respectively coupled to true and complement inputs of a sense amplifier circuit. Such Y-line groups may number only one Y-line, or may number more than one Y-line. Many types of memory cells may be used, such as various passive element cells and EEPROM cells, in both 2D or 3D memory arrays. Such arrays may be configured as a memory to store data, or configured to perform threshold logic, or configured as a content addressable memory array.
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Citations
53 Claims
- 1. A non-volatile memory cell array comprising within a first array block a first plurality of X-lines configured to be individually selected in a write mode of operation and configured to be simultaneously selected in a read mode of operation, and each associated with a first Y-line group numbering at least one Y-line and also associated with a second Y-line group numbering at least one Y-line.
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26. A method of operating a non-volatile memory array comprising:
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programming individual memory cells associated with a first X-line group of at least one X-line within a first array block and further associated with a first Y-line group of at least one Y-line within the first array block until a desired first aggregate memory cell read current is obtained when simultaneously selecting all the first group of X-lines and all the first group of Y-lines, at least one of the first X-line group and first Y-line group including more than one such X-line or Y-line, and each of the first X-line aroup associated with a second Y-line group numbering at least one Y-line; and reading the memory array by simultaneously selecting all the first group of X-lines and all the first group of Y-lines and generating a signal responsive to the first aggregate memory cell read current. - View Dependent Claims (27, 28, 29, 30, 31, 32, 33, 34)
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35. An integrated circuit comprising:
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a memory array including; a plurality of X-lines disposed on at least one layer of the memory array; a plurality of Y-lines disposed on at least one other layer of the memory array; a plurality of non-volatile memory cells, each coupled to an associated one of the plurality of X-lines and an associated one of the plurality of Y-lines; an X-line selection circuit for selecting within a first array block at least a first X-line group of at least two X-lines when in a read mode, and for selecting a lesser number of X-lines within at least the first X-line group when in a write mode; and a Y-line selection circuit for simultaneously selecting within the first array block in the read mode a first Y-line group of at least one Y-line and a second Y-line group of at least one Y-line, and for respectively coupling the selected first and second Y-line groups to respective first and second inputs of an associated sense amplifier circuit; wherein the associated sense amplifier circuit is responsive to an aggregate signal from memory cells associated with both the selected first X-line group and the selected first Y-line group, and responsive to an aggregate signal from memory cells associated with both the selected first X-line group and the selected second Y-line group. - View Dependent Claims (36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47)
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48. An integrated circuit comprising:
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a memory array including; a plurality of X-lines disposed on at least one layer of the memory array; a plurality of Y-lines disposed on at least one other layer of the memory array; a plurality of non-volatile memory cells, each coupled to an associated one of the plurality of X-lines and an associated one of the plurality of Y-lines; means for programming individual memory cells associated with a first X-line group of at least one X-line within a first array block and further associated with a first Y-line group of at least one Y-line within the first array block until a desired aggregate memory cell read current is obtained when simultaneously selecting all the first group of X-lines and all the first group of Y-lines, at least one of the first X-line group and first Y-line group including more than one such X-line or Y-line, and each of the first X-line group associated with a second Y-line group numbering at least one Y-line; and means for reading the memory array by simultaneously selecting all the first group of X-lines and all the first group of Y-lines and generating a signal responsive to the aggregate memory cell read signal conveyed on the first group of Y-lines. - View Dependent Claims (49, 50, 51, 53)
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52. The integrated circuit of clami 51 wherein the memory array comprises anti-fuse memory cells.
Specification