Selective operation of a multi-state non-volatile memory system in a binary mode

• US 7,177,184 B2
• Filed: 04/05/2004
• Issued: 02/13/2007
• Est. Priority Date: 09/17/2001
• Status: Expired due to Term

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk Corporation (Western Digital Corporation)
• Inventors: Chen, Jian
• Primary Examiner(s): LE, THONG QUOC
• Application Number:
  US10/818,926
• Publication Number:
  US 20040190337A1
• Time in Patent Office: 1,044 Days
• Field of Search: 365/185.03, 365/185.24, 365/185.11, 365/185.14, 365/185.28
• US Class Current: 365/185.03
• CPC Class Codes: G11C 11/56 using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
• CPC Class Codes: G11C 11/5621 using charge storage in a floating gate
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/12 Programming voltage switching circuits
• CPC Class Codes: G11C 2211/5641 Multilevel memory having cells with different number of storage levels

Abstract

A flash non-volatile memory system that normally operates its memory cells in multiple storage states is provided with the ability to operate some selected or all of its memory cell blocks in two states instead. The two states are selected to be the furthest separated of the multiple states, thereby providing an increased margin during two state operation. This allows faster programming and a longer operational life of the memory cells being operated in two states when it is more desirable to have these advantages than the increased density of data storage that multi-state operation provides.

Claims

1. In a memory system, a method of controllably operating a plurality of blocks of re-programmable non-volatile memory cells in either at least four threshold level states or exactly two threshold level states, wherein said at least four threshold level states are spaced apart across a memory cell operating threshold window and said exactly two threshold level states are those of the four threshold level states that are maximally separated from each other within the operating threshold window, and wherein designations of whether the individual blocks of memory cells operate with at least four threshold level states or exactly two threshold level states are maintained within the memory system and accessed by physical addresses used to access the blocks.

2. The method of claim 1, wherein the memory cells within at least one of the plurality of blocks is operated in said exactly two threshold level states and the memory cells within at least another one of the plurality of blocks is operated in said at least four threshold level states.

3. The method of claim 2, wherein a file allocation table (FAT) table of blocks of memory in which user data are stored is written into memory cells of said at least one of the plurality of blocks that is operated in said exactly two threshold levels, and the user data is stored in memory cells of said at least another one of the plurality of blocks that is operated in said at least four threshold level states.

4. The method of claim 1, wherein at least one of said plurality of blocks of memory cells is initially operated in said at least four threshold level states until a number of erase/programming cycles of said at least one block reaches a predetermined amount, upon which said at least one block is then operated in said at least two threshold level states.

5. In a memory system having a plurality of blocks of non-volatile memory cells that individually stores more than one bit of data in one of at least four threshold level states that are spaced apart across an operating threshold window, a method of operating the memory system comprising storing one bit of data in the memory cells of at least one of the blocks in only two of said at least four threshold level states that are furthest displaced from each other within the operating threshold window, wherein a spread of threshold level values of the memory cells within the individual threshold level states is greater in the case where one bit of data are stored in the memory cells than in the case where more than one bit of data are stored.

6. The method of claim 5, which additionally comprises reading data from the individual cells of said at least some of the blocks that are stored in said only two of the four threshold level states by use of a threshold reference having a value intermediate of others of said at least four threshold level states than said only two threshold level states furthest displaced from each other.

7. In a memory system having a plurality of blocks of non- volatile memory cells that individually stores more than one bit of data in one of at least four threshold level states that are spaced apart across an operating threshold window, a method of operating the memory system comprising storing one bit of data in the memory cells of at least one of the blocks in oly two of said at least four threshold level states that are furthest displaced from each other within the operating threshold window, wherein a spread of threshold level values of the memory cells within the individual threshold level states is greater in the case where one bit of data are stored in the memory cells than in the case where more than one bit of data are stored wherein one of said only two threshold level states furthest displaced from each other is an erased state within a negative region of the operating threshold window and said read threshold reference is a non-zero positive voltage, and which additionally comprises reading data from the induvidual cells of said at least some of the blocks that are stored in said only two of the four threshold level states by use of a threshold reference having a value intermediate of others of said at least four threshold level states than said only two threshold level states furthest displaced from each other.

8. In a memory stystem having a plurality of blocks of non- volatile memory cells that individually stores more than one bit of data in one of at least four threshold level states that are spaced apart across an operating threshold window, wherein the memory system is a NAND system, a method of operating the memory system comprising storing one bit of data in the memory cells of at least one of the blocks in only two of said at least four threshold level states that are furthest displaced from each other within the operating threshold window, wherein a spread of threshold level values of the memory cells within the individual threshold level states is greater in the case where one bit of data are stored in the memory cells than in the case where more than one bit of data are stored.

9. In a flash non-volatile memory system with memory cells connected in a NAND arrangement, wherein at least two bits are normally programmed in sequence into individual ones of the memory cells from at least two different pages of data, a method of programming only one bit into some of the system'"'"'s memory cells comprising programming one bit from one of said at least two pages into individual ones of said some of the system'"'"'s memory cells in the same manner as when normally programmed as one of two bits but without allowing programming of the second bit from the other of said at least two pages into said some of the system'"'"'s memory cells.

10. A method of operating a memory system having a plurality of units of re-programmable non-volatile semiconductor memory cells that are erased prior to reprogramming, which comprises:

programming user data received from outside the memory system into the memory cells of a first group of one or more units by a first plurality of threshold level states, wherein the first plurality of threshold level states are spaced apart across an operating threshold window of the memory cells, and

programming other data that are rewritten more frequently than the user data into the memory cells of a second group of one or more units by a second plurality of threshold level states less than the first plurality, the second plurality of threshold level states including those of the first plurality of threshold level states that are maximally separated from each other within the operating threshold window.

11. The method of claim 10, wherein the other data include a system file allocation table (FAT).

12. The method of claim 10, wherein the other data include overhead information generated within the memory system to manage operation thereof.

13. A method of operating a memory system having a plurality of units of re-programmable non-volatile semiconductor memory cells, comprising:

initially storing data in the individual memory cells of at least one of the units within one of a first plurality of threshold level states spaced apart across an operating threshold window,

monitoring when the usage of said at least one of the units reaches an endurance limit of a number of erase/programming cycles, and

thereafter storing data in the individual memory cells of said at least one of the units within one of a second plurality of threshold level states spaced apart across the operating threshold window, the second plurality of threshold level states being less than the first plurality of threshold level states.

14. The method of claim 13, additionally comprising maintaining counts of the number of erase/programming cycles of the individual units, wherein said at least one unit operates with the first plurality of threshold level states until the cycle count of said at least one unit reaches a preset number, after which said at least one unit operates with the second plurality of threshold level states.

15. The method of claim 13, wherein the second plurality of threshold level states are limited to those of the first plurality of threshold level states that are maximally separated from each other across the operating window.

16. A method of operating a memory system having a plurality of units of re-programmable non-volatile semiconductor memory cells that are erased prior to reprogramming, which comprises:

programming data into the memory cells of a first group of one or more units into a first plurality of threshold level states by a succession of pulses that incrementally increase in magnitude by a first difference, wherein the first plurality of threshold level states are spaced apart across an operating threshold window of the memory cells, and

programming data into the memory cells of a second group of one or more units into a second plurality of threshold level states less than the first plurality of threshold level states by a succession of pulses that incrementally increase in magnitude by a second difference larger than the first difference,

whereby a spread of threshold levels within the second plurality of threshold level states is wider than a spread of threshold levels within the first plurality of threshold level states.

17. The method of claim 16, wherein the second plurality of threshold level states are limited to two threshold level states that are maximally separated from each other within the operating threshold window.

18. A memory system, comprising:

an array of non-volatile memory cells having re-programmable charge storage elements organized into blocks that are simultaneously erasable, and

programming circuits that program two or more bits of data into the individual charge storage elements from two or more pages of user data in corresponding two or more successive programming operations to cause levels of charge stored on the individual charge storage elements to be within one of at least four non-overlapping ranges but that limits the programming of the charge storage elements in a designated one or more of the blocks to control charge levels stored on the charge storage elements therein to only two of the at least four ranges by implementing only one of the two or more successive programming operations, thereby to store only one bit of data per charge storage element in the designated one or more blocks wherein said only two of the at least four ranges have a margin therebetween extending across intervening of the at least four ranges.

19. The memory system of claim 18, wherein the programming circuits implement said one of the two or more successive programming operations on the charge storage elements of the designated one or more blocks by applying successive programming pulses having differences in magnitude greater than that between successive programming pulses applied during the two or more successive programming operations that cause levels of charge stored on the individual charge storage elements to be within one of at least four non-overlapping ranges.

20. The memory system of claim 18, wherein the programming circuits program system operating data into the designated one or more blocks that are rewritten more frequently than the user data.

21. The memory system of claim 20, wherein the system operating data programmed into the designated one or more blocks include a system file allocation table (FAT).

22. The memory system of claim 18, wherein the programming circuits dynamically identify a given block as one of the designated blocks in response to the given block reaching an endurance limit of a number of erase/programming cycles.

23. The memory system of claim 18, wherein the plurality of memory cells include a plurality of series strings of at least eight memory cell transistors that extend in one direction across a semiconductor substrate between bit lines and a voltage source, and word lines extending across the strings in a second direction across the substrate, the first and second directions being orthogonal to each other, the charge storage elements being located within the strings of memory cell transistors where crossed by the word lines.

24. The memory system of claim 18, wherein the programming circuits include a state machine.

25. The memory system of claim 18, wherein the charge storage elements are electrically conductive floating gates.