Semiconductor memory device, display device, and portable electronic apparatus

• US 7,177,188 B2
• Filed: 02/11/2004
• Issued: 02/13/2007
• Est. Priority Date: 02/12/2003
• Status: Expired due to Fees

• Current Assignee: Sharp Kabushiki Kaisha (Hon Hai Precision Industry Co., Ltd.)
• Original Assignee: Sharp Kabushiki Kaisha (Hon Hai Precision Industry Co., Ltd.)
• Inventors: Yaoi, Yoshifumi, Iwase, Yasuaki, Nawaki, Masaru, Morikawa, Yoshinao, Tanaka, Kenichi, Iwata, Hiroshi, Shibata, Akihide
• Primary Examiner(s): NGUYEN, TAN
• Application Number:
  US10/775,254
• Publication Number:
  US 20040160828A1
• Time in Patent Office: 1,098 Days
• Field of Search: 365/185.05
• US Class Current: 365/185.05
• CPC Class Codes: G11C 16/0408 comprising cells containing floating gate transistors G11C16/0483, G11C16/0491 take precedence
• CPC Class Codes: H01L 29/40114 the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
• CPC Class Codes: H01L 29/40117 the electrodes comprising a charge-trapping insulator
• CPC Class Codes: H01L 29/7923 Programmable transistors with more than two possible different levels of programmation

Abstract

A semiconductor memory device includes: a memory cell having a gate electrode formed on a semiconductor layer via a gate insulating film, a channel region disposed below the gate electrode, a diffusion region disposed on both sides of the channel region and having a conductive type opposite to that of the channel region, and memory functional units formed on both sides of the gate electrode and having a function of retaining charges; and an amplifier, the memory cell and the amplifier being connected to each other so that an output of the memory cell is inputted to the amplifier.

Claims

1. A semiconductor memory device including:

an amplifier; and

first and second paired memory cells each having a gate electrode formed on a semiconductor layer via a gate insulating film, a channel region disposed below the gate electrode, a diffusion region disposed on both sides of the channel region and having a conductive type opposite to that of the channel region, and memory functional units formed on both sides of the gate electrode and having a function of retaining charges and being an insulator containing a silicon nitride film;

wherein outputs of the paired memory cells are inputted to the amplifier.

2. The semiconductor memory device according to claim 1, wherein the memory cell is rewritable in first and second storing states of different amounts of charges accumulated in the memory functional units and, at the time of reading, one of the paired memory cells is in the first storing state, and the other memory cell is allowed to operate in the second storing state.

3. The semiconductor memory device according to claim 1, wherein one or more transistors are connected in series to the memory cell.

4. The semiconductor memory device according to claim 1, wherein the memory functional unit is formed so that at least a part of the memory functional unit overlaps with a part of the diffusion region.

5. The semiconductor memory device according to claim 1, wherein the memory functional unit includes a film having the function of retaining charges and whose surface is substantially parallel with the surface of a gate insulating film.

6. The semiconductor memory device according to claim 5, wherein the memory functional unit has an insulating film separating the film having the function of retaining charges from the channel region or semiconductor layer and the insulating film is thicker than the gate insulating film and has a thickness of 20 nm or less.

7. A display device in which the semiconductor memory device according to claim 1 is incorporated.

8. A portable electronic apparatus in which the semiconductor memory device according to claim 1 is incorporated.

9. A semiconductor memory device including:

an amplifier; and

first and second paired memory cells each having a gate electrode formed on a semiconductor layer via a gate insulating film, a channel region disposed below the gate electrode, a diffusion region disposed on both sides of the channel region and having a conductive type opposite to that of the channel region, and memory functional units formed on both sides of the gate electrode and having a function of retaining charges;

wherein outputs of the paired memory cells are inputted to the amplifier, and wherein the gate electrodes of the paired memory cells integrally function as a word line, and the paired memory cells integrally share the memory functional units at both sides of the gate electrodes.

10. A semiconductor memory device including:

an amplifier; and

first and second paired memory cells each having a gate electrode formed on a semiconductor layer via a gate insulating film, a channel region disposed below the gate electrode, a diffusion region disposed on both sides of the channel region and having a conductive type opposite to that of the channel region, and memory functional units formed on both sides of the gate electrode and having a function of retaining charges;

wherein outputs of the paired memory cells are inputted to the amplifier, wherein the memory cell is rewritable in first and second storing states of different amounts of charges accumulated in each of two memory functional units formed on both sides of a gate electrode, and wherein at the time of reading, the storing states of the two memory functional units belonging to the same memory cell are the same and information stored in memory functional units belonging to one of the paired memory cells is different from information stored in memory functional units belonging to the other of the paired memory cells.

11. A semiconductor memory device including:

an amplifier; and

first and second paired memory cells each having a gate electrode formed on a semiconductor layer via a gate insulating film, a channel region disposed below the gate electrode, a diffusion region disposed on both sides of the channel region and having a conductive type opposite to that of the channel region, and memory functional units formed on both sides of the gate electrode and having a function of retaining charges;

wherein outputs of the paired memory cells are inputted to the amplifier, and wherein a plurality of paired memory cell are connected to the amplifier, the paired memory cell are connected to different word lines, and an output of a predetermined paired memory cell is inputted to the amplifier by selection of one word line.

12. A semiconductor memory device including:

an amplifier; and

first and second paired memory cells each having a gate electrode formed on a semiconductor layer via a gate insulating film, a channel region disposed below the gate electrode, a diffusion region disposed on both sides of the channel region and having a conductive type opposite to that of the channel region, and memory functional units formed on both sides of the gate electrode and having a function of retaining charges;

wherein outputs of the paired memory cells are inputted to the amplifier, wherein the memory functional unit includes a film having the function of retaining charges and whose surface is substantially parallel with the surface of a gate insulating film, and wherein the film having the function of retaining charges is disposed substantially parallel with the side face of the gate electrode.

13. A semiconductor memory device including:

an amplifier; and

first and second paired memory cells each having a gate electrode formed on a semiconductor layer via a gate insulating film, a channel region disposed below the gate electrode, a diffusion region disposed on both sides of the channel region and having a conductive type opposite to that of the channel region, and memory functional units formed on both sides of the gate electrode and having a function of retaining charges;

wherein outputs of the paired memory cells are inputted to the amplifier

wherein the memory functional unit includes a film having the function of retaining charges and whose surface is substantially parallel with the surface of a gate insulating film, and wherein the memory functional unit has an insulating film for separating the film having the function of retaining charges from the channel region or semiconductor layer, and the insulating film is thinner than the gate insulating film and has a thickness of 0.8 nm or more.