Nonvolatile semiconductor memory having plural data storage portions for a bit line connected to memory cells

• US 7,177,196 B2
• Filed: 02/14/2002
• Issued: 02/13/2007
• Est. Priority Date: 09/28/1999
• Status: Expired due to Term

• Current Assignee: Toshiba Memory Corporation (Kioxia Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Takeuchi, Ken, Tanaka, Tomoharu, Shibata, Noboru
• Primary Examiner(s): Ho; Hoai V.
• Application Number:
  US10/073,999
• Publication Number:
  US 20020114207A1
• Time in Patent Office: 1,825 Days
• Field of Search: 365/185.22, 365/185.17, 365/185.18, 365/185.28, 365/185.11, 365/185.01
• US Class Current: 365/185.22
• CPC Class Codes: G11C 11/5621 using charge storage in a floating gate
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 11/5642 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/08 Address circuits; Decoders; Word-line control circuits
• CPC Class Codes: G11C 16/12 Programming voltage switching circuits
• CPC Class Codes: G11C 16/24 Bit-line control circuits
• CPC Class Codes: G11C 16/3418 Disturbance prevention or evaluation; Refreshing of disturbed memory data
• CPC Class Codes: G11C 16/3431 Circuits or methods to detect disturbed nonvolatile memory cells, e.g. which still read as programmed but with threshold less than the program verify threshold or read as erased but with threshold greater than the erase verify threshold, and to reverse the disturbance via a refreshing programming or erasing step
• CPC Class Codes: G11C 16/3445 Circuits or methods to verify correct erasure of nonvolatile memory cells
• CPC Class Codes: G11C 16/3459 Circuits or methods to verify correct programming of nonvolatile memory cells
• CPC Class Codes: G11C 2211/5621 Multilevel programming verification
• CPC Class Codes: G11C 2211/5642 Multilevel memory with buffers, latches, registers at input or output
• CPC Class Codes: G11C 2211/5643 Multilevel memory comprising cache storage devices
• CPC Class Codes: G11C 2211/5649 Multilevel memory with plate line or layer, e.g. in order to lower programming voltages
• CPC Class Codes: G11C 2211/565 Multilevel memory comprising elements in triple well structure
• CPC Class Codes: G11C 2216/14 Circuits or methods to write a page or sector of information simultaneously into a nonvolatile memory, typically a complete row or word line in flash memory
• CPC Class Codes: G11C 7/1051 Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits

Abstract

Data having three values or more is stored in a memory cell in a nonvolatile manner. A data circuit has a plurality of storage circuits. One of the plurality of storage circuits is a latch circuit. Another one of the plurality of storage circuits is a capacitor. The latch circuit and the capacitor function to temporarily store program/read data having two bits or more. Data held by the capacitor is refreshed using the latch circuit if data variation due to leakage causes a program. As a result, the data circuit does not become large in size even if multi-level data is used.

Claims

1. A nonvolatile semiconductor memory comprising:

a first string including a first memory cell and a first select transitor connected in series;

a second string line including a second memory cell and a second select transistor connected in series;

a first bit line connected to said first string line;

a second bit line connected to said second string line, being different from said first bit line;

a common node connected to one ends of said first and second bit lines, and

a common latch circuit connected to said common node,

wherein

said first and second memory cells are programmed substantially simultaneously; and

while a program voltage is supplied to said second memory cell, a verify read operation to verify whether said first memory cell has been programmed sufficiently, is carried out by said common latch circuit, and while said program voltage is supplied to said first memory cell, a verify read operation to verify whether said second memory cell has been programmed sufficiently, is carried out by said latch circuit.

2. A nonvolatile semiconductor memory according to claim 1,

wherein

while said program voltage is supplied to said second memory cell, program data of said second memory cell is held by said second bit line, and

while said program voltage is supplied to said first memory cell, program data of said first memory cell is held by said first bit line.

3. The nonvolatile semiconductor memory according to claim 2, wherein said first memory cell and said second memory cell are connected to different word lines.

4. The nonvolatile semiconductor memory according to claim 1, wherein said first memory cell and said second memory cell are connected to different word lines.

5. A nonvolatile semiconductor memory comprising:

a first string line including a first memory and a first select transistor connected in series;

a second string line including a second memory cell and a second select transistor connected in series;

a first bit line connected to said first string line;

a second bit connected to said second string line, being different from said first bit line;

a common node connnected to one ends of said first and second bit lines; and

a common latch circuit connected to said common node,

wherein

said first and second memory cells are programmed substantially simultaneously;

while a program voltage is supplied to said first memory cell, program data of said memory cell is held by second bit line, and while said program voltage is supplied to said second memory cell, the program data of said first memory cell held by said first bit line is latched in said common latch circuit and a verify read operation to verify whether said first memory cell has been programmed sufficiently, is carried out by said common latch circuit;

while said program is supplied to said first memory cell, program data of said first memory cell is held by said first bit line, and while said program voltage is supplied to said first memory cell, the program of data said second memory cell held by said second memory cell has been programmed sufficiently, is carried out by said common latch circuit.

6. The nonvolatile semiconductor memory according to claim 5, wherein said first memory cell and said second memory cell are connected to different word lines.

7. A nonvolatile semiconductor memory comprising:

a first string line including a first memory cell and a first select transistor connected in series;

a first bit line connected to said first string line;

a second bit line, being different from said first bit line;

a common node connected to one ends of said first and second bit lines latching program/read data; and

a common latch circuit connected to said common node,

wherein

while a program voltage is supplied to said first memory cell, program data of said first memory cell is held by at least one of said first and second bit lines;

after said program voltage is supplied to said first memory cell, said common latch circuit is electrically connected to said second bit line and the program data of said first memory cell held by said second bit line is latched in said common latch circuit; and

a verify read operation to verify whether said first memory cell has been sufficiently programmed, is carried out using said program data latched in said common latch circuit.

8. The nonvolatile semiconductor memory according to claim 7, wherein

while said program/read data is held by said first or second bit line, a potential of a bit line adjacent to said first or second bit line is set at a fixed potential.

9. The nonvolatile semiconductor memory according to claim 8, wherein said fixed potential is a ground potential or a power supply potential.

13. The nonvolatile semiconductor memory according to claim 9, wherein

while said program/read data is held by said first or second signal line, a potential of a signal a potential of a signal line adjacent to said first or second signal line is set at a fixed potential.

10. A nonvolatile semiconductor memory comprising:

a first string line including a first memory cell and a first select transistor connected in series;

a first bit line connected to said first string line;

a second string line including a second memory cell and a second select transistor connected in series;

a third bit line connected to said second string line;

a fourth bit line;

a common node connected to one ends of said first, second, third and fourth bit lines, latching program/read data of at least one of said first and second memory cells; and

a common latch circuit connected to said common node,

wherein

said first, second, third and fourth bit lines are different from each other;

said first and second memory cells are programmed substantially simultaneously, program data of said first memory cell is held by at least one of said first and second bit lines, and program data of said second memory cell is held by at least one of said third and fourth bit lines while a program voltage is supplied to said first and second memory cells;

a verify read operation to verify whether said first memory cell has been sufficiently programmed, is carried out by said common latch circuit, and program data of said second memory cell is held by said fourth bit line while conducting the verify read operation of said first memory cell; and

said common latch circuit and said fourth bit line are electrically connected to each other, after the program data of said second memory cell held by said fourth bit line is latched in said common latch circuit, a verify read operation to verify whether said second memory cell has been sufficiently programmed, is carried out using the program data of said second memory cell held by said common latch circuit, and while conducting a verify read operation of said second memory cell, the program data of said first memory cell is held by said second bit line.

11. A nonvolatile semiconductor memory comprising:

a first memory cell section including a first memory cell;

a first signal line connected to said first memory cell section;

a second signal line;

a third memory cell section including a third memory cell;

a third signal line connected to said third memory cell section;

a fourth signal line; and

a data circuit connected to one ends of said first, second, third and forth signal lines, and including a latch circuit said latch circuit latching program/read data of at least one of said first and third memory cells;

wherein

said first and third memory cells are programmed substantially simultaneously, program data of said first memory cell is held by at least one of said first and second signal lines, and program data of said third memory cell is held by at least one of said third and fourth signal lines while a program voltage is supplied to said first and second memory cells;

a verify read operation to verify whether said first memory cell has been sufficiently programmed, is carried out by said latch circuit, and program data of said third memory cell is held by said fourth signal line while conducting the verify read operation of said first memory cell; and

said data circuit and said fourth signal line are electrically connected to each other, after the program data of said third memory cell held by said fourth signal line is latched in said latch circuit, a verify read operation to verify whether said third memory cell has been sufficiently programmed, is carried out using the program data of said third memory cell held by said latch circuit, and while conducting a verify read operation of said third memory cell, the program data of said first memory cell is held by said second signal line.

12. The nonvolatile semiconductor memory according to claim 11, wherein

said first and third memory cells are connected to a same word line.