Negative bias temperature instability (NBTI) preconditioning of matched devices
First Claim
1. A method of compensating for accumulated data-dependent post-manufacture shift in a characteristic of one or more of a pair of matched devices within an integrated circuit, said shift giving rise to a mismatch in the characteristic between the pair of matched devices, the method comprising:
- preconditioning the matched devices to cause an initial shift in the characteristic in each of the matched devices and to thereby reduce an expected magnitude of any further lifetime shift in the characteristic of either matched device.
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Accused Products
Abstract
An accumulated data-dependent post-manufacture shift in a characteristic of one or more of a pair of matched devices within an integrated circuit may cause a mismatch in the characteristic between the pair of matched devices. This mismatch may be reduced by preconditioning the matched devices to cause an initial shift in the characteristic in each of the matched devices and to thereby reduce an expected magnitude of any further lifetime shift in the characteristic of either matched device. In an exemplary sense amplifier circuit having matched cross-coupled PMOS load devices, a data dependent threshold mismatch between the PMOS devices resulting from a Negative Bias Temperature Instability (NBTI) effect may be reduced by biasing both of the matched PMOS devices so that both experience an initial NBTI Vt shift, and so that any expected further Vt shift in either device over the product lifetime is reduced. Consequently the amount of threshold mismatch that may subsequently develop over the product lifetime is likewise reduced.
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Citations
58 Claims
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1. A method of compensating for accumulated data-dependent post-manufacture shift in a characteristic of one or more of a pair of matched devices within an integrated circuit, said shift giving rise to a mismatch in the characteristic between the pair of matched devices, the method comprising:
preconditioning the matched devices to cause an initial shift in the characteristic in each of the matched devices and to thereby reduce an expected magnitude of any further lifetime shift in the characteristic of either matched device. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23)
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24. A circuit comprising:
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first and second matched devices which are susceptible to an accumulated data-dependent post-manufacture shift in a characteristic of one or more of the matched devices, said shift giving rise to a mismatch in the characteristic between the matched devices; and a preconditioning circuit for subjecting the matched devices to a particular condition for a length of time sufficient to cause an initial shift in the characteristic in each of the matched devices and to thereby reduce an expected magnitude of any further lifetime shift in the characteristic of either matched device. - View Dependent Claims (25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47)
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48. An integrated circuit comprising:
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memory elements; a sense amplifier circuit for sensing data stored in associated memory elements, said sense amplifier including first and second matched devices which are susceptible to an accumulated data-dependent post-manufacture shift in a characteristic of one or more of the matched devices, said shift giving rise to a mismatch in the characteristic between the matched devices; and a preconditioning circuit for subjecting the matched devices to a particular condition for a length of time sufficient to cause an initial shift in the characteristic in each of the matched devices and to thereby reduce an expected magnitude of any further lifetime shift in the characteristic of either matched device. - View Dependent Claims (49, 50, 51, 52, 53, 54, 55)
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56. A computer readable encoding of a semiconductor integrated circuit design, the computer readable encoding comprising:
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one or more media encoding a representation of a memory circuit that includes plural pairs of bit lines, memory cells coupled to respective ones of the bit line pairs; the one or more media further encoding a representation of a sense amplifier circuit coupled to one or more respective ones of the bit line pairs for sensing data stored in associated memory elements, said sense amplifier circuit including first and second matched devices which are susceptible to an accumulated data-dependent post-manufacture shift in a characteristic of one or more of the matched devices, said shift giving rise to a mismatch in the characteristic between the matched devices; and the one or more media further encoding a representation of a preconditioning circuit for subjecting the matched devices to a particular condition for a length of time sufficient to cause an initial shift in the characteristic in each of the matched devices and to thereby reduce an expected magnitude of any further lifetime shift in the characteristic of either matched device. - View Dependent Claims (57, 58)
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Specification