Circuit and method for operating a delay-lock loop in a power saving manner

• US 7,177,208 B2
• Filed: 03/11/2005
• Issued: 02/13/2007
• Est. Priority Date: 03/11/2005
• Status: Expired due to Fees

• Current Assignee: Round Rock Research LLC
• Original Assignee: Micron Technology, Inc.
• Inventors: Smith, Scott, Gomm, Tyler
• Primary Examiner(s): Nguyen; Tuan T.
• Application Number:
  US11/077,641
• Publication Number:
  US 20060221759A1
• Time in Patent Office: 704 Days
• Field of Search: 365/194, 365/233, 365/193, 365/227
• US Class Current: 365/194
• CPC Class Codes: G11C 11/4076 Timing circuits for regeneration management G11C11/406
• CPC Class Codes: G11C 2207/2227 Standby or low power modes
• CPC Class Codes: G11C 7/22 Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
• CPC Class Codes: G11C 7/222 Clock generating, synchronizing or distributing circuits within memory device

Abstract

A control circuit for a delay-lock loop having a delay line and a phase detector is used in a memory device. In a standby mode, the control circuit isolates a reference clock signal from the delay-lock loop to save power unless a clock signal generated by the loop is needed for a memory operation. However, the reference signal is periodically coupled to the delay line for a sufficient period to achieve a locked condition. As a result, the phase of the output signal from delay-lock loop can be quickly locked to the phase of the reference signal when a memory operation is to occur during a normal operating mode. When transitioning between the standby mode and the normal operating mode, the control circuit couples the reference clock signal to the delay line for at least a predetermined period of time.

Claims

1. A memory device, comprising:

a row address circuit operable to receive and decode row address signals applied to external address terminals of the memory device;

a column address circuit operable to receive and decode column address signals applied to the external address terminals;

a memory cell array operable to store data written to and read from the array at a location determined by the decoded row address signals and the decoded column address signals;

a read data path circuit operable to couple read data signals from the memory cell array to external data terminals of the memory device, the read data signals being applied to the external data terminals responsive to a read data strobe signal;

a write data path circuit operable to couple write data signals from the external data terminals of the memory device responsive to a write data strobe signal, the write data signals being coupled to the memory cell array;

a command decoder operable to decode a plurality of command signals applied to respective external command terminals of the memory device, the command decoder being operable to generate control signals corresponding to the decoded command signals;

a delay-lock loop operable to generate either the write data strobe signal or the read data strobe signal from an internal clock signal, the delay-loop comprising a delay line receiving a reference clock signal and generating an output clock signal from which either the write data strobe signal or the read data strobe signal is derived, the delay-lock loop further comprising a phase detector receiving the reference clock signal and the output clock signal and controlling the delay of the delay line responsive thereto; and

a loop control circuit selectively coupling the reference clock signal to the delay line, the loop control circuit being operable when the memory device is operating in a normal operating mode to continuously couple the reference clock signal to the delay line, the loop control circuit being operable when the memory device is operating in a standby mode to enter a standby period in which the reference clock signal is isolated from the delay line, and, while in the standby period, periodically couple the reference clock signal to the delay line for an update period of sufficient duration to allow the delay-lock loop to achieve a locked condition.

2. The memory device of claim 1 wherein the loop control circuit is operable to couple the reference clock signal to the delay line for at least a predetermined period when the memory device enters the normal operating mode.

3. The memory device of claim 1 wherein the loop control circuit is operable in the standby mode to receive a signal indicative of a bank of memory cells in the memory device becoming active, and to couple the reference clock signal to the delay line responsive to the signal indicative of a bank of memory cells in the memory device becoming active.

4. The memory device of claim 1 wherein the loop control circuit is operable in the standby mode to receive a signal indicative of whether the delay-lock loop is in a locked or an unlocked condition, the loop control circuit being operable when entering the standby mode to immediately isolate the reference clock signal from the delay line responsive to receiving the signal indicating that the delay-lock loop is in a locked condition, the loop control circuit further being operable when entering the standby mode to continue coupling the reference clock signal to the delay line for a predetermined period before isolating the reference clock signal from the delay line responsive to receiving the signal indicating that the delay-lock loop is in an unlocked condition.

5. The memory device of claim 1 wherein the loop control circuit is further operable to selectively enable and disable the phase detector while coupling the reference clock signal to the delay line when the memory device is operating in the standby mode.

6. The memory device of claim 5 wherein the memory device is operable in an on die termination mode, and wherein the loop control circuit is further operable in the standby mode to disable the phase detector in the on die termination mode while coupling the reference clock signal to the delay line.

7. The memory device of claim 1 wherein the memory device comprises a dynamic random access memory device.

8. A memory device, comprising:

a row address circuit operable to receive and decode row address signals applied to external address terminals of the memory device;

a column address circuit operable to receive and decode column address signals applied to the external address terminals;

a memory cell array operable to store data written to and read from the array at a location determined by the decoded row address signals and the decoded column address signals;

a read data path circuit operable to couple read data signals from the memory cell array to external data terminals of the memory device, the read data signals being applied to the external data terminals responsive to a read data strobe signal;

a write data path circuit operable to couple write data signals from the external data terminals of the memory device responsive to a write data strobe signal, the write data signals being coupled to the memory cell array;

a command decoder operable to decode a plurality of command signals applied to respective external command terminals of the memory device, the command decoder being operable to generate control signals corresponding to the decoded command signals;

a delay-lock loop operable to generate either the write data strobe signal or the read data strobe signal from an internal clock signal, the delay-loop comprising a delay line receiving a reference clock signal and generating an output clock signal from which either the write data strobe signal or the read data strobe signal is derived, the delay-lock loop further comprising a phase detector receiving the reference clock signal and the output clock signal and controlling the delay of the delay line responsive thereto; and

a loop control circuit selectively coupling the reference clock signal to the delay line, the loop control circuit being operable when the memory device is operating in a normal operating mode to continuously couple the reference clock signal to the delay line, the loop control circuit being operable when the memory device is operating in a standby mode to enter a standby period in which the reference clock signal is isolated from the delay line, and, while in the standby period, periodically couple the reference clock signal to the delay line for an update period of sufficient duration to allow the delay-lock loop to achieve a locked condition.

9. The memory device of claim 8 wherein the loop control circuit is operable to couple the reference clock signal to the delay line for at least a predetermined period when the memory device enters the normal operating mode.

10. The memory device of claim 8 wherein the loop control circuit is operable in the standby mode to receive a signal indicative of a bank of memory cells in the memory device becoming active, and to couple the reference clock signal to the delay line responsive to the signal indicative of a bank of memory cells in the memory device becoming active.

11. The memory device of claim 8 wherein the loop control circuit is operable in the standby mode to receive a signal indicative of whether the delay-lock loop is in a locked or an unlocked condition, the loop control circuit being operable when entering the standby mode to immediately isolate the reference clock signal from the delay line responsive to receiving the signal indicating that the delay-lock loop is in a locked condition, the loop control circuit further being operable when entering the standby mode to continue coupling the reference clock signal to the delay line for a predetermined period before isolating the reference clock signal from the delay line responsive to receiving the signal indicating that the delay-lock loop is in an unlocked condition.

12. The memory device of claim 8 wherein the loop control circuit is further operable to selectively enable and disable the phase detector while coupling the reference clock signal to the delay line when the memory device is operating in the standby mode.

13. The memory device of claim 12 wherein the memory device is operable in an on die termination mode, and wherein the loop control circuit is further operable in the standby mode to disable the phase detector in the on die termination mode while coupling the reference clock signal to the delay line.

14. The memory device of claim 8 wherein the memory device comprises a dynamic random access memory device.

15. A processor-based system, comprising

a processor having a processor bus;

an input device coupled to the processor through the processor bus adapted to allow data to be entered into the computer system;

an output device coupled to the processor through the processor bus adapted to allow data to be output from the computer system; and

a memory device coupled to the processor bus adapted to allow data to be stored, the memory device comprising;

a row address circuit operable to receive and decode row address signals applied to external address terminals of the memory device;

a column address circuit operable to receive and decode column address signals applied to the external address terminals;

a memory cell array operable to store data written to and read from the array at a location determined by the decoded row address signals and the decoded column address signals;

a read data path circuit operable to couple read data signals from the memory cell array to external data terminals of the memory device, the read data signals being applied to the external data terminals responsive to a read data strobe signal;

a write data path circuit operable to couple write data signals from the external data terminals of the memory device responsive to a write data strobe signal, the write data signals being coupled to the memory cell array;

a command decoder operable to decode a plurality of command signals applied to respective external command terminals of the memory device, the command decoder being operable to generate control signals corresponding to the decoded command signals;

a delay-lock loop operable to generate either the write data strobe signal or the read data strobe signal from an internal clock signal, the delay-loop comprising a delay line receiving a reference clock signal and generating an output clock signal from which either the write data strobe signal or the read data strobe signal is derived, the delay-lock loop further comprising a phase detector receiving the reference clock signal and the output clock signal and controlling the delay of the delay line responsive thereto; and

a loop control circuit selectively coupling the reference clock signal to the delay line, the loop control circuit being operable when the memory device is operating in a normal operating mode to continuously couple the reference clock signal to the delay line, the loop control circuit being operable when the memory device is operating in a standby mode to enter a standby period in which the reference clock signal is isolated from the delay line, and, while in the standby period, periodically couple the reference clock signal to the delay line for an update period of sufficient duration to allow the delay-lock loop to achieve a locked condition.

16. The processor-based system of claim 15 wherein the loop control circuit is operable to couple the reference clock signal to the delay line for at least a predetermined period when the memory device enters the normal operating mode.

17. The processor-based system of claim 15 wherein the loop control circuit is operable in the standby mode to receive a signal indicative of a bank of memory cells in the memory device becoming active, and to couple the reference clock signal to the delay line responsive to the signal indicative of a bank of memory cells in the memory device becoming active.

18. The processor-based system of claim 15 wherein the loop control circuit is operable in the standby mode to receive a signal indicative of whether the delay-lock loop is in a locked or an unlocked condition, the loop control circuit being operable when entering the standby mode to immediately isolate the reference clock signal from the delay line responsive to receiving the signal indicating that the delay-lock loop is in a locked condition, the loop control circuit further being operable when entering the standby mode to continue coupling the reference clock signal to the delay line for a predetermined period before isolating the reference clock signal from the delay line responsive to receiving the signal indicating that the delay-lock loop is in an unlocked condition.

19. The processor-based system of claim 15 wherein the loop control circuit is further operable to selectively enable and disable the phase detector while coupling the reference clock signal to the delay line when the memory device is operating in the standby mode.

20. The processor-based system of claim 19 wherein the memory device is operable in an on die termination mode, and wherein the loop control circuit is further operable in the standby mode to disable the phase detector in the on die termination mode while coupling the reference clock signal to the delay line.

21. The processor-based system of claim 15 wherein the memory device comprises a dynamic random access memory device.

22. A processor-based system, comprising

a processor having a processor bus;

an input device coupled to the processor through the processor bus adapted to allow data to be entered into the computer system;

an output device coupled to the processor through the processor bus adapted to allow data to be output from the computer system; and

a memory device coupled to the processor bus adapted to allow data to be stored, the memory device comprising;

a row address circuit operable to receive and decode row address signals applied to external address terminals of the memory device;

a column address circuit operable to receive and decode column address signals applied to the external address terminals;

a memory cell array operable to store data written to and read from the array at a location determined by the decoded row address signals and the decoded column address signals;

a read data path circuit operable to couple read data signals from the memory cell array to external data terminals of the memory device, the read data signals being applied to the external data terminals responsive to a read data strobe signal;

a write data path circuit operable to couple write data signals from the external data terminals of the memory device responsive to a write data strobe signal, the write data signals being coupled to the memory cell array;

a command decoder operable to decode a plurality of command signals applied to respective external command terminals of the memory device, the command decoder being operable to generate control signals corresponding to the decoded command signals;

a delay-lock loop operable to generate either the write data strobe signal or the read data strobe signal from an internal clock signal, the delay-loop comprising a delay line receiving a reference clock signal and generating an output clock signal from which either the write data strobe signal or the read data strobe signal is derived, the delay-lock loop further comprising a phase detector receiving the reference clock signal and the output clock signal and controlling the delay of the delay line responsive thereto; and

a loop control circuit selectively coupling the reference clock signal to the delay line, the loop control circuit being operable when the memory device is operating in a normal operating mode to continuously couple the reference clock signal to the delay line, the loop control circuit being operable when the memory device is operating in a standby mode to enter a standby period in which the reference clock signal is isolated from the delay line, and, while in the standby period, periodically couple the reference clock signal to the delay line for an update period of sufficient duration to allow the delay-lock loop to achieve a locked condition.

23. The processor-based system of claim 22 wherein the loop control circuit is operable to couple the reference clock signal to the delay line for at least a predetermined period when the memory device enters the normal operating mode.

24. The processor-based system of claim 22 wherein the loop control circuit is operable in the standby mode to receive a signal indicative of a bank of memory cells in the memory device becoming active, and to couple the reference clock signal to the delay line responsive to the signal indicative of a bank of memory cells in the memory device becoming active.

25. The processor-based system of claim 22 wherein the loop control circuit is operable in the standby mode to receive a signal indicative of whether the delay-lock loop is in a locked or an unlocked condition, the loop control circuit being operable when entering the standby mode to immediately isolate the reference clock signal from the delay line responsive to receiving the signal indicating that the delay-lock loop is in a locked condition, the loop control circuit further being operable when entering the standby mode to continue coupling the reference clock signal to the delay line for a predetermined period before isolating the reference clock signal from the delay line responsive to receiving the signal indicating that the delay-lock loop is in an unlocked condition.

26. The processor-based system of claim 22 wherein the loop control circuit is further operable to selectively enable and disable the phase detector while coupling the reference clock signal to the delay line when the memory device is operating in the standby mode.

27. The processor-based system of claim 26 wherein the memory device is operable in an on die termination mode, and wherein the loop control circuit is further operable in the standby mode to disable the phase detector in the on die termination mode while coupling the reference clock signal to the delay line.

28. The processor-based system of claim 22 wherein the memory device comprises a dynamic random access memory device.