Transistor layout configuration for tight-pitched memory array lines
First Claim
1. An integrated circuit comprising:
- a memory array disposed above a dielectric layer, said memory array comprising a plurality of memory blocks, said memory array further comprising a plurality of array lines, each respective array line traversing horizontally across a respective memory block;
a plurality of array line driver circuits disposed beneath the dielectric layer, each array line driver circuit comprising a first driver transistor of a first conductivity type coupled to drive a respective array line; and
a plurality of connection areas disposed between adjacent memory blocks, each connection area comprising a respective conductive path from a respective array line associated with an adjacent memory block to a respective electrode on a lower interconnection level, said respective electrode being coupled to a respective array line driver circuit;
wherein half of the array line driver circuits associated with a given connection area are disposed at least partially beneath the memory block to one side of the given connection area, and the other half of the array line driver circuits associated with the given connection area are disposed at least partially beneath the memory block to the other side of the given connection area.
3 Assignments
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Accused Products
Abstract
A multi-headed word line driver circuit incorporates bent-gate transistors to reduce the pitch otherwise achievable for interfacing to tightly-pitched array lines. In certain exemplary embodiments, a three-dimensional memory array includes multiple memory blocks and array lines traversing horizontally across at least one memory block. Vertical active area stripes are disposed beneath a first memory block, and a respective plurality of bent-gate electrodes intersects each respective active area stripe to define individual source/drain regions. Every other source/drain region is coupled to a bias node for the active area stripe, and remaining source/drain regions are respectively coupled to a respective array line associated with the first memory block, thereby forming a respective first driver transistor for the respective array line. In certain embodiments, a respective plurality of complementary array line driver circuits is disposed on each side of a connection area between adjacent memory blocks, and each such driver circuit is responsive to a single driver input node.
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Citations
25 Claims
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1. An integrated circuit comprising:
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a memory array disposed above a dielectric layer, said memory array comprising a plurality of memory blocks, said memory array further comprising a plurality of array lines, each respective array line traversing horizontally across a respective memory block; a plurality of array line driver circuits disposed beneath the dielectric layer, each array line driver circuit comprising a first driver transistor of a first conductivity type coupled to drive a respective array line; and a plurality of connection areas disposed between adjacent memory blocks, each connection area comprising a respective conductive path from a respective array line associated with an adjacent memory block to a respective electrode on a lower interconnection level, said respective electrode being coupled to a respective array line driver circuit; wherein half of the array line driver circuits associated with a given connection area are disposed at least partially beneath the memory block to one side of the given connection area, and the other half of the array line driver circuits associated with the given connection area are disposed at least partially beneath the memory block to the other side of the given connection area. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18)
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19. A method comprising:
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providing a memory array disposed above a dielectric layer, said memory array comprising a plurality of memory blocks, said memory array further comprising a plurality of array lines, each respective array line traversing horizontally across a respective memory block; providing a plurality of array line driver circuits disposed beneath the dielectric layer, each array line driver circuit comprising a first driver transistor of a first conductivity type; and providing a plurality of connection areas disposed between adjacent memory blocks, each connection area comprising a respective conductive path from a respective array line associated with an adjacent memory block to a respective electrode on a lower interconnection level, said respective electrode being coupled to a respective driver circuit; wherein half of the array line driver circuits associated with a given connection area are disposed at least partially beneath the memory block to one side of the given connection area, and the other half of the array line driver circuits associated with the given connection area are disposed at least partially beneath the memory block to the other side of the given connection area. - View Dependent Claims (20)
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21. An integrated circuit comprising:
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a memory array comprising a plurality of memory blocks, each memory block comprising a respective plurality of array lines; and a plurality of array line driver circuits, each array line driver circuit coupled to an associated array line through a respective vertical connection formed in an associated one of a plurality of connection areas disposed between adjacent memory blocks; wherein half of the array line driver circuits associated with a given connection area are disposed at least partially beneath the memory block to one side of the given connection area, and the other half of the array line driver circuits associated with the given connection area are disposed at least partially beneath the memory block to the other side of the given connection area. - View Dependent Claims (22, 23, 24, 25)
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Specification