Transistor layout configuration for tight-pitched memory array lines

• US 7,177,227 B2
• Filed: 05/29/2006
• Issued: 02/13/2007
• Est. Priority Date: 03/31/2005
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk 3D LLC (Western Digital Corporation)
• Inventors: Scheuerlein, Roy E., Petti, Christopher J., Bandyopadhyay, Abhijit, Kumar, Tanmay
• Primary Examiner(s): Dinh; Son T.
• Application Number:
  US11/420,787
• Publication Number:
  US 20060221758A1
• Time in Patent Office: 260 Days
• Field of Search: 365/230.06, 365/51, 365/63
• US Class Current: 365/230.06
• CPC Class Codes: G11C 5/02 Disposition of storage elements, e.g. in the form of a matrix array
• CPC Class Codes: G11C 5/063 Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
• CPC Class Codes: G11C 8/08 Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines
• CPC Class Codes: G11C 8/14 Word line organisation; Word line lay-out
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H10B 12/09 with simultaneous manufacture of the peripheral circuit region and memory cells
• CPC Class Codes: H10B 12/50 Peripheral circuit region structures

Abstract

A multi-headed word line driver circuit incorporates bent-gate transistors to reduce the pitch otherwise achievable for interfacing to tightly-pitched array lines. In certain exemplary embodiments, a three-dimensional memory array includes multiple memory blocks and array lines traversing horizontally across at least one memory block. Vertical active area stripes are disposed beneath a first memory block, and a respective plurality of bent-gate electrodes intersects each respective active area stripe to define individual source/drain regions. Every other source/drain region is coupled to a bias node for the active area stripe, and remaining source/drain regions are respectively coupled to a respective array line associated with the first memory block, thereby forming a respective first driver transistor for the respective array line. In certain embodiments, a respective plurality of complementary array line driver circuits is disposed on each side of a connection area between adjacent memory blocks, and each such driver circuit is responsive to a single driver input node.

Claims

1. An integrated circuit comprising:

a memory array disposed above a dielectric layer, said memory array comprising a plurality of memory blocks, said memory array further comprising a plurality of array lines, each respective array line traversing horizontally across a respective memory block;

a plurality of array line driver circuits disposed beneath the dielectric layer, each array line driver circuit comprising a first driver transistor of a first conductivity type coupled to drive a respective array line; and

a plurality of connection areas disposed between adjacent memory blocks, each connection area comprising a respective conductive path from a respective array line associated with an adjacent memory block to a respective electrode on a lower interconnection level, said respective electrode being coupled to a respective array line driver circuit;

wherein half of the array line driver circuits associated with a given connection area are disposed at least partially beneath the memory block to one side of the given connection area, and the other half of the array line driver circuits associated with the given connection area are disposed at least partially beneath the memory block to the other side of the given connection area.

2. The integrated circuit as recited in claim 1 further comprising a plurality of driver input nodes, each coupled to a respective driver circuit on each side of a given connection area.

3. The integrated circuit as recited in claim 2 wherein each of the plurality of driver input nodes is coupled to a respective plurality M of array line driver circuits on each side of a given connection area.

4. The integrated circuit as recited in claim 2 wherein each of the plurality of driver input nodes is coupled to a respective driver circuit on each side of at least three connection areas, thereby each driver input node being coupled to at least six such array line driver circuits.

5. The integrated circuit as recited in claim 4 further comprising a decoder circuit having as outputs the plurality of driver input nodes, said decoder circuit disposed along one side of the memory array.

6. The integrated circuit as recited in claim 1 wherein:

the memory array comprises a three-dimensional memory array; and

each array line comprises an array line segment on each of two memory layers of the three-dimensional memory array.

7. The integrated circuit as recited in claim 1 wherein each memory block includes interleaved array lines, approximately half of which are coupled to associated array line driver circuits by way of the connection area on one side of the memory block, and the remaining ones are coupled to associated array line driver circuits by way of the connection area on the other side of the memory block.

8. The integrated circuit as recited in claim 7 wherein, in a given memory block, the array lines coupled to associated array line driver circuits by way of the connection area on one side of the given memory block are common with array lines in an adjacent memory block thereto.

9. The integrated circuit as recited in claim 1 wherein each array line driver circuit further comprises a second driver transistor of a second conductivity type opposite the first conductivity type, each respective second driver transistor coupled to drive the respective array line.

10. The integrated circuit as recited in claim 9 wherein each of said first driver transistors comprises a bent-gate transistor.

11. The integrated circuit as recited in claim 9 wherein, for the array line driver circuits disposed to one side of a given connection area:

the respective first driver transistors are arranged in a first column; and

the respective second driver transistors are arranged in a second column.

12. The integrated circuit as recited in claim 11 further comprising a plurality of driver input nodes, wherein a respective driver circuit on each side of a connection area is coupled to a respective driver input node.

13. The integrated circuit as recited in claim 12 wherein each of the plurality of driver input nodes is coupled to a respective plurality M of array line driver circuits on each side of three connection areas, thereby resulting in a plurality 6*M of array line driver circuits responsive to a single associated driver input node.

14. The integrated circuit as recited in claim 9 wherein:

said plurality of array lines comprise word lines; and

each memory block includes interleaved word lines, approximately half of which are coupled to associated array line driver circuits by way of the connection area on one side of the memory block, and the remaining ones are coupled to associated array line driver circuits by way of the connection area on the other side of the memory block.

15. The integrated circuit as recited in claim 14 wherein:

the memory array comprises a three-dimensional memory array; and

each word line in a given memory block comprises a word line segment associated with each of two memory planes within the given memory block.

16. The integrated circuit as recited in claim 15:

wherein the plurality of first driver transistors comprise NMOS transistors and the plurality of second driver transistors comprise PMOS transistors;

wherein each of the plurality of driver input nodes is coupled to a respective plurality M of array line driver circuits on each side of at least three connection areas; and

wherein, in a given memory block, the word lines coupled to associated array line driver circuits by way of the connection area on one side of the given memory block are shared with word lines in an adjacent memory block thereto.

17. The integrated circuit as recited in claim 16 wherein:

the respective first driver transistors within each plurality M of array line driver circuits disposed to one side of a given connection area are arranged in a first column; and

the respective second driver transistors within each plurality M of array line driver circuits disposed to one side of a given connection area are arranged in a second column closer to the given connection area than the first column.

18. The integrated circuit as recited in claim 16 further comprising a decoder circuit having as outputs the plurality of driver input nodes, said decoder circuit disposed along one side of the memory array.

19. A method comprising:

providing a memory array disposed above a dielectric layer, said memory array comprising a plurality of memory blocks, said memory array further comprising a plurality of array lines, each respective array line traversing horizontally across a respective memory block;

providing a plurality of array line driver circuits disposed beneath the dielectric layer, each array line driver circuit comprising a first driver transistor of a first conductivity type; and

providing a plurality of connection areas disposed between adjacent memory blocks, each connection area comprising a respective conductive path from a respective array line associated with an adjacent memory block to a respective electrode on a lower interconnection level, said respective electrode being coupled to a respective driver circuit;

wherein half of the array line driver circuits associated with a given connection area are disposed at least partially beneath the memory block to one side of the given connection area, and the other half of the array line driver circuits associated with the given connection area are disposed at least partially beneath the memory block to the other side of the given connection area.

20. The method as recited in claim 19 further comprising providing a plurality of driver input nodes, each coupled to a respective plurality M of array line driver circuits on each side of a given connection area.

21. An integrated circuit comprising:

a memory array comprising a plurality of memory blocks, each memory block comprising a respective plurality of array lines; and

a plurality of array line driver circuits, each array line driver circuit coupled to an associated array line through a respective vertical connection formed in an associated one of a plurality of connection areas disposed between adjacent memory blocks;

wherein half of the array line driver circuits associated with a given connection area are disposed at least partially beneath the memory block to one side of the given connection area, and the other half of the array line driver circuits associated with the given connection area are disposed at least partially beneath the memory block to the other side of the given connection area.

22. The integrated circuit as recited in claim 21 further comprising:

a plurality of driver input nodes, each coupled to a respective driver circuit on each side of at least three connection areas; and

a decoder circuit having as outputs the plurality of driver input nodes, said decoder circuit disposed along one side of the memory array.

23. The integrated circuit as recited in claim 22 wherein:

the memory array comprises a three-dimensional memory array; and

each array line comprises an array line segment on each of more than one memory layer of the three-dimensional memory array.

24. The integrated circuit as recited in claim 23 wherein:

each memory block includes interleaved array lines, approximately half of which are coupled to associated array line driver circuits by way of the connection area on one side of the memory block, and the remaining ones are coupled to associated array line driver circuits by way of the connection area on the other side of the memory block; and

the array lines coupled to associated array line driver circuits by way of the connection area on one side of a memory block are common with array lines in an adjacent memory block thereto.

25. A computer-readable medium encoding an integrated circuit, said encoded integrated circuit as recited in claim 21.