Chipset support for managing hardware interrupts in a virtual machine system

• US 7,177,967 B2
• Filed: 09/30/2003
• Issued: 02/13/2007
• Est. Priority Date: 09/30/2003
• Status: Expired due to Fees

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Anderson, Andrew V., Neiger, Gilbert, Bennett, Steven M., Uhlig, Richard, Jeyasingh, Stalinselvaraj, Kagi, Alain, Cota-Robles, Erik
• Primary Examiner(s): Ray; Gopal C.
• Application Number:
  US10/676,890
• Publication Number:
  US 20050080970A1
• Time in Patent Office: 1,232 Days
• Field of Search: 710260-269, 710/200, 710/40, 710/48, 710/49, 712/224, 712/244, 718/1, 718/100, 718/103, 718/108, 711/6, 711/151, 711/203, 700/1
• US Class Current: 710/260
• CPC Class Codes: G06F 13/24 using interrupt G06F13/32 takes precedence
• CPC Class Codes: G06F 9/45533 Hypervisors; Virtual machine monitors
• CPC Class Codes: G06F 9/4812 by interrupt, e.g. masked

Abstract

In one embodiment, an apparatus includes a set of multiplex blocks coupled with an interrupt controller and multiple interrupt request lines, and a virtual machine monitor block (VMM) coupled to the set of multiplex blocks. Each multiplex block corresponds to a distinct interrupt request line. Each multiplex block is to route the interrupt request signal received via the corresponding interrupt request line either to the interrupt controller or the VMM block depending on a current configuration value of this multiplex block.

Claims

1. A system comprising:

an interrupt controller;

one or more interrupt request lines;

one or more multiplex blocks couplable with the interrupt controller and the one or more interrupt request lines, each of the one or more multiplex blocks corresponding to a distinct one of the one or more interrupt request lines; and

a virtual machine monitor (VMM) block couplable to the one or more multiplex blocks and a processor;

wherein each of the one or more multiplex blocks is to route an interrupt request signal received via a corresponding interrupt request line either to the interrupt controller or the VMM block depending on a current configuration value of said each of the one or more multiplex blocks.

2. The system of claim 1 wherein the current configuration value of said each of the one or more multiplex blocks requires that the interrupt request signal be routed to the interrupt controller if a device generating the interrupt request signal is managed by a currently operating virtual machine (VM).

3. The system of claim 1 wherein the current configuration value of said each of the one or more multiplex blocks requires that the interrupt request signal be routed to the VMM block if a device generating the interrupt request signal is not managed by a currently operating virtual machine (VM).

4. The system of claim 1 wherein the VMM block comprises a mask register to store mask information pertaining to one or more interrupt request signals routed to the VMM block.

5. The system of claim 4 wherein the VMM block is to assert an internal signal if one of the one or more routed interrupt request signals is asserted and is not masked, and to send the internal signal to the processor to cause a transition of control to a VMM.

6. The system of claim 5 wherein the VMM block is further to combine the internal signal with an external signal generated by an external signal source prior to sending the internal signal to the processor.

7. The system of claim 6 wherein:

the external signal is a non-maskable interrupt (NMI) signal; and

the external signal source is a NMI source.

8. The system of claim 6, wherein the internal signal is combined with the external signal using an OR operator.

9. The system of claim 4 wherein the mask register of the VMM block is configurable by a VMM.

10. The system of claim 1 wherein the VMM block comprises a status register to store status of each interrupt request signal routed to the VMM block.

11. The system of claim 1 wherein the interrupt controller has a read and write access path to a plurality of registers of the interface controller.

12. The system of claim 1 wherein:

the one or more multiplex blocks are configured by a VMM.

13. An apparatus comprising:

one or more multiplex blocks couplable with an interrupt controller and one or more interrupt request lines, each of the one or more multiplex blocks corresponding to a distinct one of the one or more interrupt request lines; and

a virtual machine monitor (VMM) block couplable to the one or more multiplex blocks,

wherein each of the one or more multiplex blocks is to route an interrupt request signal received via a corresponding interrupt request line either to the interrupt controller or the VMM block depending on a current configuration value of said each of the one or more multiplex blocks.

14. The apparatus of claim 13 wherein the current configuration value of said each of the one or more multiplex blocks requires that the interrupt request signal be routed to the interrupt controller if a device generating the interrupt request signal is managed by a currently operating virtual machine (VM).

15. The apparatus of claim 13 wherein the current configuration value of said each of the one or more multiplex blocks requires that the interrupt request signal be routed to the VMM block if a device generating the interrupt request signal is not managed b a currently operating virtual machine (VM).

16. A system comprising:

a processor; and

a memory, coupled to the processor, to store instructions, which when executed by the processor, cause the processor to identify one or more interrupt request lines that are coupled to one or more devices managed by a virtual machine (VM), configure one or more multiplex blocks to route interrupt request signals that are managed by the VM on the one or more interrupt request lines to an interrupt controller, configure one or more multiplex blocks to route interrupt request signals that are not managed by the VM to a virtual machine monitor (VMM) block, and generate a request to transfer control to the VM.

17. The system of claim 16 wherein the instructions, when executed by the processor, cause the processor further to configure a mask register in the VMM block to cause masking of interrupt requested signals routed to the VMM block.

18. The system of claim 16 wherein the instructions, when executed by the processor, cause the processor further to restore a state saved during a previous operation of the VM in the interrupt controller.