Card system with erase tagging hierarchy and group based write protection

• US 7,177,975 B2
• Filed: 04/09/2001
• Issued: 02/13/2007
• Est. Priority Date: 11/04/1998
• Status: Expired due to Fees

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk Corporation (Western Digital Corporation)
• Inventors: Toombs, Thomas N., Holtzman, Micky
• Primary Examiner(s): KIM, HONG CHONG
• Application Number:
  US09/829,146
• Publication Number:
  US 20010016887A1
• Time in Patent Office: 2,136 Days
• Field of Search: 711/103, 711170-173, 711/115, 711/5, 711/4, 711/150, 711/156, 365/185.33, 365/185.29, 365/185.11
• US Class Current: 711/103
• CPC Class Codes: G06F 12/1433 for a module or a part of a module
• CPC Class Codes: G06F 2212/2022 Flash memory
• CPC Class Codes: G11C 16/102 External programming circuits, e.g. EPROM programmers; In-circuit programming or reprogramming; EPROM emulators
• CPC Class Codes: G11C 16/22 Safety or protection circuits preventing unauthorised or accidental access to memory cells

Abstract

A low cost data storage and communication system is disclosed. The low cost data storage and communication system has a host and at least one card connected to the host. A voltage negotiator located in the system for determining a common operating voltage range that is a common denominator of all independent operating voltage ranges of all of the cards connected to the system. In addition, a novel feature of partitioning the memory storages of the card is also disclosed. This feature provides the host the ability to simultaneously erase any combination of sectors in a single erase group, or any combination of the entire erase groups. Another feature feature provided by this novel method of partitioning the memory storages is the ability to write protect any combination of memory groups in the card.

Claims

1. A memory system, comprising:

a plurality of memory groups, each of said memory groups comprising a plurality of memory sectors, each of said memory sectors comprising a plurality of memory cells, wherein the number of memory sectors in each memory group is configurable;

a plurality of group tags, each of said group tags corresponds to one of said memory groups, each of said group tags indicating whether the memory cells under the corresponding memory group are erasable; and

a plurality of sector tags, each of said sector tags corresponds to a memory sector, each of said sector tags indicating whether the memory cells under the corresponding memory sector are erasable,

wherein all the memory cells belonging to one memory sector are erasable when either the corresponding sector tag or the corresponding group tag of the memory sector is set;

wherein any combination of memory sectors in a memory group can be simultaneously erased, and any combination of the memory groups can be simultaneously erased; and

wherein in response to too few tags being set, a received erase command is aborted.

2. The memory system according to claim 1, wherein the corresponding sectors in each memory group is calculated in real time.

3. The memory system according to claim 1, wherein said memory system is a flash memory.

4. The memory system according to claim 1, wherein said sector tags and said group tags are settable by a host to which the memory system is connected.

5. The memory system according to claim 4, wherein said sector tags and said group tags are set in response to a host command.

6. The memory system according to claim 5, wherein set ones of said sector tags and said group tags are deselected in response to a host command.

7. The memory system according to claim 1, wherein the number of memory sectors in each memory group is configurable by a host to which the memory system is connected.