Method, system and memory controller utilizing adjustable read data delay settings

• US 7,177,998 B2
• Filed: 01/18/2006
• Issued: 02/13/2007
• Est. Priority Date: 04/24/2001
• Status: Expired due to Term

• Current Assignee: Rampart Asset Management LLC
• Original Assignee: Rambus Inc.
• Inventors: Perego, Richard E., Tsern, Ely K., Hampel, Craig E., Ware, Frederick A.
• Primary Examiner(s): NGUYEN, THAN VINH
• Application Number:
  US11/335,029
• Publication Number:
  US 20060129776A1
• Time in Patent Office: 391 Days
• Field of Search: None
• US Class Current: 711/167
• CPC Class Codes: G06F 1/06 Clock generators producing several clock signals G06F1/08 - G06F1/14 take precedence
• CPC Class Codes: G06F 1/105 in which the distribution is at least partially optical
• CPC Class Codes: G06F 1/12 Synchronisation of different clock signals provided by a plurality of clock generators
• CPC Class Codes: G06F 13/1684 using multiple buses
• CPC Class Codes: G06F 13/1689 Synchronisation and timing concerns synchronisation on a memory bus G06F13/4234
• CPC Class Codes: G06F 13/1694 Configuration of memory controller to different memory types
• CPC Class Codes: G06F 13/4086 Bus impedance matching, e.g. termination
• CPC Class Codes: G06F 13/4243 with synchronous protocol
• CPC Class Codes: G06F 3/0604 Improving or facilitating administration, e.g. storage management
• CPC Class Codes: G06F 3/0658 Controller construction arrangements
• CPC Class Codes: G06F 3/0673 Single storage device
• CPC Class Codes: G11C 11/4076 Timing circuits for regeneration management G11C11/406
• CPC Class Codes: G11C 11/409 Read-write [R-W] circuits
• CPC Class Codes: G11C 11/4096 Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
• CPC Class Codes: G11C 29/02 Detection or location of defective auxiliary circuits, e.g. defective refresh counters
• CPC Class Codes: G11C 29/022 in I/O circuitry
• CPC Class Codes: G11C 29/023 in clock generator or timing circuitry
• CPC Class Codes: G11C 29/028 with adaption or trimming of parameters
• CPC Class Codes: G11C 29/50008 of impedance
• CPC Class Codes: G11C 29/50012 of timing
• CPC Class Codes: G11C 5/063 : Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
• CPC Class Codes: G11C 7/04 : with means for avoiding disturbances due to temperature effects
• CPC Class Codes: G11C 7/1051 : Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
• CPC Class Codes: G11C 7/1072 : for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
• CPC Class Codes: G11C 7/1078 : Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
• CPC Class Codes: G11C 7/22 : Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
• CPC Class Codes: G11C 7/222 : Clock generating, synchronizing or distributing circuits within memory device
• CPC Class Codes: G11C 8/18 : Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals

Abstract

A method, system and memory controller that uses adjustable read data delay settings. The memory controller includes control transmit circuitry, data reception circuitry and timing circuitry. The control circuitry transmits a control signal to multiple memory devices via a shared control signal path. The data reception circuitry receives data signals from the memory devices via respective data signal paths. The timing circuitry delays reception of data signals on each of the data signal paths by a respective time interval that is based, at least in part, on a time required for the control signal to propagate on the control signal path from the memory controller to a respective one of the memory devices.

Claims

1. A system comprising:

a first memory device and a second memory device;

a control signal path coupled to the first memory device and the second memory device such that a read command propagating on the control signal path propagates past the first memory device before reaching the second memory device and such that a first propagation time required for the read command to propagate on the control signal path from the memory controller to the first memory device is different than a second propagation time required for the read command to propagate on the control signal path from the memory controller to the second memory device;

a first signal line coupled to the first memory device to convey first data output from the first memory device in response to the read command;

a second signal line coupled to the second memory device to convey second data output from the second memory device in response to the read command; and

a memory controller including;

a first circuit to receive the first data from the first memory device after delaying for a first time interval that is based, at least in part, on the first propagation time; and

a second circuit to receive the second data from the second memory device after delaying for a second time interval that is based, at least in part, on the second propagation time.

2. The system of claim 1, wherein the first time interval corresponds to a sum of the first propagation time and a time required for the first data to propagate on the first signal line from the first memory device to the memory controller.

3. The system of claim 1, wherein:

the first circuit comprises a first phase offset selection circuit to select a first clock signal from a plurality of phase-distributed clock signals to be a timing reference for reception of the first data on the first signal line; and

the second circuit comprises a second phase offset selection circuit to select a second clock signal from the plurality of phase-distributed clock signals to be a timing reference for reception of the second data on the second signal line.

4. The system of claim 1, further comprising:

a first termination component coupled to the first signal line, wherein the first termination component is disposed on the first memory device;

a second termination component coupled to the second signal line, wherein the second termination component is disposed on the second memory device; and

a termination component coupled to the control signal path.

5. The system of claim 1, further comprising a timing signal path coupled to the first memory device and the second memory device, the timing signal path to carry a timing signal that indicates a first time at which the read command propagating on the control signal path is sampled by the first memory device, and wherein the timing signal indicates a second time at which the read command propagating on the control signal path is sampled by the second memory device.

6. The system of claim 1, further comprising:

a third signal line to carry a first timing signal that indicates a time at which the first data conveyed on the first signal line is sampled by the memory controller; and

a fourth signal line to carry a second timing signal that indicates a time at which the second data conveyed on the second signal line is sampled by the memory controller.

7. A memory controller comprising:

control transmit circuitry to transmit a control signal to a plurality of memory devices via a shared control signal path, the shared control signal path being coupled to each of the memory devices at a different point along its length such that respective times required for the control signal to propagate from the memory controller to the memory devices are different;

data receive circuitry to receive data signals from the memory devices via respective data signal paths; and

timing circuitry to delay reception of data signals on each of the data signal paths by a respective time interval that is based, at least in part, on the time required for the control signal to propagate on the control signal path from the memory controller to a respective memory device of the memory devices.

8. The memory controller of claim 7, wherein the respective time interval corresponds to a sum of the time required for the control signal to propagate on the control signal path from the memory controller to the respective memory device and a time required for data signals to propagate on the data signal path from the respective memory device to the memory controller.

9. The memory controller of claim 7, wherein the timing circuitry comprises a plurality of phase offset selection circuits, each phase offset selection circuit of the plurality of phase offset selection circuits to select a clock signal of a plurality of phase-distributed clock signals to be a timing reference for receiving data conveyed on a respective one of the data signal paths.

12. The memory controller of claim 9, wherein each phase offset selection circuit of the plurality of phase offset selection circuits comprises a multiplexer to select the clock signal of the plurality of phase-distributed clock signals in response to a respective control signal.

10. The memory controller of 9, further comprising clock generation circuitry to generate the plurality of phase-distributed clock signals, the plurality of phase-distributed clock signals having phase offsets that are substantially evenly distributed within a cycle time of a first clock signal.

11. The memory controller of claim 10, wherein the clock generation circuitry comprises a phase-locked loop circuit to generate the first clock signal based on a reference clock signal that has a lower frequency than the first clock signal.

13. A method of controlling memory devices in a system that includes at least a first memory device and a second memory device, the method comprising:

transmitting a control signal to the memory devices via a control signal path, wherein the control signal propagates past the first memory device and the second memory devices in sequence, and wherein a first propagation time required for the control signal to propagate on the control signal path to the first memory device is different from a second propagation time required for the control signal to propagate on the control signal path to the second memory device;

receiving a first data signal from the first memory device via a first data signal path after delaying for a first time interval, wherein the first time interval is based, at least in part on the first propagation time; and

receiving a second data signal from the second memory device via a second data signal path after delaying for a second time interval, wherein the second time interval is based, at least in part on the second propagation time.

14. The method of claim 13, wherein receiving the first data signal from the first memory device via the first data signal path after delaying for a first time interval comprises delaying reception of the first data signal according to a sum of the first propagation time and a time required for the first data signal to propagate from the first memory device to the memory controller via the first data signal path.

15. The method of claim 13, wherein receiving the second data signal from the second memory device via the second data signal path after delaying for the second time interval comprises delaying reception of the second data signal according to a sum of the second propagation time and a time required for the second data signal to propagate from the second memory device to the memory controller via the second data signal path.

16. The method of claim 13, wherein receiving the first data signal from the first memory device via the first data signal path after delaying for the first time interval comprises selecting a receive clock signal from a plurality of phase-distributed clock signals such that the receive clock signal includes a phase offset that corresponds to the first time interval.

17. The method of claim 16, further comprising generating the plurality of phase-distributed clock signals in a phase-locked loop circuit.

18. A controller device comprising:

means for transmitting, via a control signal path, a control signal to a first memory device and a second memory device such that the control signal propagates past the first memory device and the second memory device in sequence, and such that a first propagation time required for the control signal to propagate on the control signal path to the first memory device is different from a second propagation time required for the control signal to propagate on the control signal path to the second memory device;

means for receiving a first data signal from the first memory device via a first data signal path after delaying for a first time interval, wherein the first time interval is based, at least in part, on the first propagation time; and

means for receiving a second data signal from the second memory device via a second data signal path after delaying for a second time interval, wherein the second time interval is based, at least in part, on the second propagation time.

19. A memory system comprising:

a memory module having a row of memory devices, including a first memory device and a second memory device, and a first termination structure;

a first data signal path coupled to the first memory device;

a second data signal path coupled to the second memory device;

a timing signal path coupled to each of the memory devices and the first termination structure, the timing signal path extending along the row of memory devices such that a timing signal propagating on the timing signal path propagates past each of the memory devices in order before reaching the first termination structure, and such that a first propagation time required for the timing signal to propagate on the timing signal path to the first memory device is different from a second propagation time required for the timing signal to propagate on the timing signal path to the second memory device; and

a memory controller, coupled to the memory module, the memory controller having first receive circuitry to receive read data on the first data path after a first time delay based, at least in part, on the first propagation time, and second receive circuitry to receive read data on the second data path after a second time delay based, at least in part, on the second propagation time.

20. The memory system of claim 19, wherein the first time delay is selected to enable the read data on the first data signal path to be transmitted by the first memory device synchronously with respect to arrival of the timing signal at the first memory device, and wherein the second time delay is selected to enable the read data on the second data signal path to be transmitted by the second memory device synchronously with respect to arrival of the timing signal at the second memory device.

21. A memory controller comprising:

a first data reception circuit to receive first read data from a first memory device via a first dedicated data signal path after delaying for a first period of time that is based, at least in part, on a first propagation time required for a timing signal to propagate on a clock line to the first memory device; and

a second data reception circuit to receive second read data from a second memory device via a second dedicated data signal path after delaying for a second period of time that is based, at least in part, on a second propagation time required for the timing signal to propagate on the clock line to the second memory device, the second propagation time being different from the first propagation time.

22. The memory controller of claim 21, wherein the first period of time is selected to enable the first read data to be transmitted by the first memory device synchronously with respect to arrival of the timing signal at the first memory device, and wherein the second period of time is selected to enable the second read data to be transmitted by the second memory device synchronously with respect to arrival of the timing signal at the second memory device.

23. The memory controller of claim 21, wherein the first period of time corresponds to a sum of the first propagation time and a time required for the first read data to propagate, via the first data signal path, from first memory device to the memory controller, and wherein the second period of time corresponds to a sum of the second propagation time and a time required for the second read data to propagate, via the second data signal path, from the second memory device to the memory controller.

24. A system comprising:

a first memory device including a first memory array;

a second memory device including a second memory array;

a first signal line coupled to the first memory device, the first signal line to convey first data retrieved from a first location in the first memory array and output from the first memory device, the first location specified by address information;

a second signal line coupled to the second memory device, the second signal line to convey second data retrieved from a second location in the second memory array and output from the second memory device, the second location specified by the address information;

a third signal line coupled to the first memory device and the second memory device, such that the address information, propagating on the third signal line, propagates past the first memory device before reaching the second memory device, and such that a first propagation time required for the address information to propagate on the third signal line to the first memory device is different than a second propagation time required for the address information to propagate to the second memory device; and

a controller including;

a first circuit to delay reception of the first data output from the first memory device by a first time interval that is based, at least in part, on the first propagation time; and

a second circuit to delay reception of the second data output from the second memory device by a second time interval that is based, at least in part, on the second propagation time.