Chemical mechanical polishing test structures and methods for inspecting the same

• US 7,179,661 B1
• Filed: 08/25/2000
• Issued: 02/20/2007
• Est. Priority Date: 12/14/1999
• Status: Expired due to Term

• Current Assignee: KLA-Tencor Corporation (KLA Corporation)
• Original Assignee: KLA-Tencor Corporation (KLA Corporation)
• Inventors: Pinto, Gustavo A., Mantalas, Lynda C., Satya, Akella V. S.
• Primary Examiner(s): Owens; Douglas W.
• Application Number:
  US09/648,095
• Time in Patent Office: 2,370 Days
• Field of Search: 257/48, 257/758, 438/11, 438/14, 438/15, 438/17, 438/18, 438/118, 438/622
• US Class Current: 438/11
• CPC Class Codes: H01L 22/34 Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line switching, multiplexing, gating devices G01R19/25; process control with lithography, e.g. dose control, G03F7/20; structures for alignment control by optical means G03F7/70633

Abstract

Disclosed is a semiconductor die having a plurality of dummy fillings positioned and sized to minimize defects during chemical mechanical polishing is disclosed. At least one of the dummy fillings is coupled to an underlying test structure. In a preferred embodiment, the semiconductor die also includes a plurality of conductive layers and a substrate. The underlying test structure includes a first layer portion formed from a first one of the plurality of conductive layer and a via coupling the first layer portion to the at least one dummy filling. In another aspect, the underlying test structure also has a via coupling the first layer portion to the substrate, and the underlying test structure comprises a plurality of layer portions and vias to form a multilevel test structure.

Claims

1. A method of fabricating a semiconductor die, comprising:

forming a first test structure on the semiconductor die, wherein at least a portion of the first test structure includes a dummy structure in a top conductive layer, wherein the dummy structure of the first test structure serves as both a dummy structure and a part of a voltage contrast structure, wherein serving as a dummy structure is defined as the dummy structure of the first test structure being part of a plurality of dummy structures that are distributed within empty spaces of the semiconductor die to facilitate an even polishing of a surface of the semiconductor die, and wherein only a portion of the dummy structures each serve as a voltage contrast structure while the other portion of dummy structures do not each serve as a voltage contrast structure; and

performing voltage contrast testing on the first test structure that serves as both a dummy structure and a voltage contrast structure to detect electrical defects within the first test structure.

2. The method of claim 1, wherein the first test structure comprises:

a substrate; and

at least one contact which couples the dummy structure to the substrate.

3. The method of claim 2, wherein the first test structure further comprises:

a first conductive layer portion over the substrate and underneath the dummy structure;

a first isolation layer between the first conductive layer portion and the substrate;

a second isolation layer between the first conductive layer portion and the dummy structure;

a first contact for coupling the substrate to the first conductive layer portion; and

a second contact for coupling the first conductive layer portion to the dummy structure.

4. The method of claim 3, wherein at least one of the first and second contacts is a redundant type contact.

5. The method of claim 3, wherein the voltage contrast testing comprises:

scanning an electron beam over the dummy structure to thereby cause electron emission from the dummy structure; and

determining that the first test structure has a defect between the substrate and the dummy structure when electron emission is impeded from the dummy structure.

6. The method of claim 5, wherein the defect is an open defect.

7. The method of claim 1, further comprising:

forming a plurality of second test structures on the semiconductor die, wherein at least a portion of each first and second test structure includes a dummy structure, wherein the second test structures permit voltage contrast testing and wherein some of the first and second test structures also include contacts for coupling its dummy structure to a substrate of the semiconductor die and others of the first and second test structures remain floating; and

performing voltage contrast testing on the first and second test structures to detect electrical defects within the first and second test structures.

8. The method of claim 7, wherein the voltage contrast testing comprises:

scanning an electron beam over the dummy structures to thereby cause electron emission from the dummy structures;

determining that a particular one of the dummy structures and its associated test structure has a defect between the substrate and the dummy structure by analyzing the electron emission from the dummy structures.

9. The method of claim 8, wherein the defect is an open defect.

10. The method of claim 1, the first test structure further comprising:

a first conductive layer portion underneath the dummy structure; and

a via coupling the first conductive layer portion to the dummy structure.

11. The method of claim 10, the first test structure further comprising:

a substrate underneath the first conductive layer portion; and

a via coupling the first conductive layer portion to the substrate.

12. The method of claim 11, wherein the via is a redundant via.

13. The method of claim 11, wherein the first test structure further comprises a plurality of stacked conductive layers and vias to form a multilevel test structure.

14. The method of claim 13, wherein at least one of the vias is a redundant via.