Flip-chip light emitting diode device without sub-mount

• US 7,179,670 B2
• Filed: 03/05/2004
• Issued: 02/20/2007
• Est. Priority Date: 03/05/2004
• Status: Active Grant

• Current Assignee: Prolight Opto Technology Corporation
• Original Assignee: Gelcore (General Electric Company)
• Inventors: Shelton, Bryan S., Venugopalan, Hari S., Arthur, Stephen, Eliashevich, Ivan, Weaver, Stanton E. Jr., Libon, Sebastien, LeBoeuf, Steven, Soules, Thomas F., Chen, Chen-Lun Hsing
• Primary Examiner(s): CRANE, SARA W
• Application Number:
  US10/794,935
• Publication Number:
  US 20050194605A1
• Time in Patent Office: 1,082 Days
• Field of Search: 438/22, 438 24- 27, 438/29, 438/108, 438/118, 257/99
• US Class Current: 438/26
• CPC Class Codes: H01L 2224/0345 Physical vapour deposition [PVD], e.g. evaporation, or sputtering
• CPC Class Codes: H01L 2224/03462 Electroplating
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/04026 Bonding areas specifically adapted for layer connectors
• CPC Class Codes: H01L 2224/05005 Structure
• CPC Class Codes: H01L 2224/05023 the whole internal layer protruding from the surface
• CPC Class Codes: H01L 2224/05027 the internal layer extending out of an opening
• CPC Class Codes: H01L 2224/0508 being stacked
• CPC Class Codes: H01L 2224/05099 Material
• CPC Class Codes: H01L 2224/05139 Silver [Ag] as principal constituent
• CPC Class Codes: H01L 2224/05144 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/05155 Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/05552 in top view
• CPC Class Codes: H01L 2224/05564 Only on the bonding interface of the bonding area
• CPC Class Codes: H01L 2224/05568 the whole external layer protruding from the surface
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/05611 Tin [Sn] as principal constituent
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 2224/13139 Silver [Ag] as principal constituent
• CPC Class Codes: H01L 2224/13144 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/13147 : Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/1357 : Single coating layer
• CPC Class Codes: H01L 2224/13599 : Material
• CPC Class Codes: H01L 2224/13639 : Silver [Ag] as principal constituent
• CPC Class Codes: H01L 2224/13644 : Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/16 : of an individual bump connector
• CPC Class Codes: H01L 2224/16225 : the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/16227 : the bump connector connecting to a bond pad of the item
• CPC Class Codes: H01L 2224/29099 : Material
• CPC Class Codes: H01L 2224/29599 : Material
• CPC Class Codes: H01L 2224/3003 : Layer connectors having different sizes, e.g. different heights or widths
• CPC Class Codes: H01L 2224/73103 : Bump and layer connectors
• CPC Class Codes: H01L 2224/73203 : Bump and layer connectors
• CPC Class Codes: H01L 2224/83193 : wherein the layer connectors are disposed on both the semiconductor or solid-state body and another item or body to be connected to the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/83203 : Thermocompression bonding, e.g. diffusion bonding, pressure joining, thermocompression welding or solid-state welding
• CPC Class Codes: H01L 2224/83205 : Ultrasonic bonding
• CPC Class Codes: H01L 2224/8321 : using a reflow oven
• CPC Class Codes: H01L 2224/8323 : Polychromatic or infrared lamp heating
• CPC Class Codes: H01L 2224/83815 : Reflow soldering
• CPC Class Codes: H01L 24/81 : using a bump connector
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00013 : Fully indexed content
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/0002 : Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/01049 : Indium [In]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/12041 : LED
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 33/38 : with a particular shape
• CPC Class Codes: H01L 33/62 : Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls

Abstract

A light emitting diode (10) has a backside and a front-side with at least one n-type electrode (14) and at least one p-type electrode (12) disposed thereon defining a minimum electrodes separation (d_electrodes). A bonding pad layer (50) includes at least one n-type bonding pad (64) and at least one p-type bonding pad (62) defining a minimum bonding pads separation (d_pads) that is larger than the minimum electrodes separation (d_electrodes). At least one fanning layer (30) interposed between the front-side of the light emitting diode (10) and the bonding pad layer (50) includes a plurality of electrically conductive paths passing through vias (34, 54) of a dielectric layer (32, 52) to provide electrical communication between the at least one n-type electrode (14) and the at least one n-type bonding pad (64) and between the at least one p-type electrode (12) and the at least one p-type bonding pad (62).

Claims

1. A method of flip chip bonding a light emitting diode to a support, the light emitting diode having front-side n-type and p-type electrodes defining a minimum electrodes separation therebetween, the method including:

disposing a dielectric layer over at least the front-side of the light emitting diode, the dielectric layer sealing the n-type and p-type electrodes;

disposing a first-type electrical contact over vias through the dielectric layer that access a first-type electrode selected from the group consisting of the p-type electrode and the n-type electrode, the first-type electrical contact extending over the dielectric layer between the vias that access the first-type electrode to define a first-type contact pad;

disposing a second-type electrical contact over one or more vias through the dielectric layer that access a second-type electrode selected from the group consisting of the other of the p-type electrode and the n-type electrode, the second-type electrical contact extending over the dielectric layer to define a second-type contact pad, the first-type contact pad and the second-type contact pad defining a minimum contact pads separation therebetween that is larger than the minimum electrodes separation; and

flip-chip bonding the first-type contact pad and the second-type contact pad to a substrate via bonding bumps disposed on at least one of the contact pads and the substrate.

2. The method as set forth in claim 1, wherein the flip-chip bonding employs a bonding process having a lateral tolerance that is larger than the minimum electrodes separation and smaller than the minimum contact pads separation.

3. The method as set forth in claim 1, wherein the disposing of the first-type electrical contact and the disposing of the second-type electrical contact each include depositing a reflow stack, the flip chip bonding including:

heating to effect reflow bonding between the contact pads and the bonding bumps.

4. The method as set forth in claim 3, wherein the heating is performed at a temperature greater than a melting point of at least one component of the reflow stack.

5. The method as set forth in claim 4, wherein the reflow stack includes a tin layer and the heating is performed at a temperature greater than about 232°

C.

6. The method as set forth in claim 3, wherein the flip chip bonding further includes:

prior to the heating, disposing an oxide-reducing flux between the contact pads and the bonding bumps of the substrate.

7. The method as set forth in claim 1, wherein the disposing of a first-type electrical contact over the vias that access the first-type electrode includes:

depositing a seed layer in the vias that access the first-type electrode; and

electroplating to fill the first vias that access the first-type electrode.

8. The method as set forth in claim 7, wherein the disposing of a first-type electrical contact over the vias that access the first-type electrode further includes:

continuing the electroplating after the vias that access the first-type electrode are filled such that the electroplated material mushrooms outside of the vias to form the first-type contact pad.

9. The method as set forth in claim 1, wherein the disposing of a first-type electrical contact over vias that access the first-type electrode includes:

depositing an electrically conductive material over the vias that access the first-type electrode and over the dielectric layer between the vias that access the first-type electrode.

10. The method as set forth in claim 1, wherein the flip chip bonding is one of conductive adhesive bonding and soldering.

11. The method as set forth in claim 1, wherein the disposing of a dielectric layer over the front-side of the light emitting diode includes:

depositing a polyamide dielectric layer having a thickness of at least 2 microns.

12. The method as set forth in claim 1, wherein the light emitting diode having front-side n-type and p-type electrodes includes a substrate wafer that has other light emitting diodes formed thereon, the method further including:

subsequent to the disposing of the dielectric layer, the disposing of the first-type electrical contact, and the disposing of the second-type electrical contact, dicing the substrate wafer to isolate at least said light emitting diode having front-side n-type and p-type electrodes from the other light emitting diodes.

13. The method as set forth in claim 12, further including:

subsequent to the disposing of the dielectric layer, the disposing of the first-type electrical contact, and the disposing of the second-type electrical contact, and prior to the dicing, performing at least one wafer-level process.

14. The method as set forth in claim 13, wherein the performing of at least one wafer level process includes at least one of:

encapsulating a back-side of the substrate wafer that is opposite the front-side, and

applying a phosphor to a back-side of the substrate wafer that is opposite the front-side.

15. The method as set forth in claim 1, wherein the flip-chip bonding of the first-type contact pad and the second-type contact pad to a substrate via bonding bumps disposed on at least one of the contact pads and the substrate includes flip chip bonding via one of:

one or more metal stacks defining bonding bumps,

one or more solderable alloy bonding bumps, and

one or more bonding bumps disposed on the contact pads, each bonding bump including a barrier metal.

16. A method of flip chip bonding a light emitting diode having front-side n-type and p-type electrodes defining a minimum electrodes separation between the n-type and p-type electrodes to mechanically secure the light emitting diode to a printed circuit board and to electrically connect the front-side n-type and p-type electrodes with printed circuitry of the printed circuit board, the method including:

disposing a dielectric layer over at least the n-type and p-type electrodes, the dielectric layer having vias passing therethrough, the vias including at least one via accessing the n-type electrode and at least one via accessing the p-type electrode;

disposing electrical contact pads over the vias and the dielectric layer, the electrical contact pads including a p-type contact pad connecting with the p-type electrode through the at least one via accessing the p-type electrode and an n-type contact pad connecting with the n-type electrode through the at least one via accessing the n-type electrode, the contact pads being arranged over the dielectric layer with a minimum contact pads separation between the p-type contact pad and the n-type contact pad that is larger than the minimum electrodes separation between the n-type and p-type electrodes; and

flip-chip bonding the contact pads to printed circuitry of the printed circuit board using bonding bumps arranged on one of the printed circuit board and the chip, the flip-chip bonding having a mechanical tolerance that is greater than the minimum electrodes separation and less than the minimum contact pads separation, there being no sub-mount arranged between the contact pads and the printed circuit board.

17. The method as set forth in claim 16, wherein the disposing of electrical contact pads includes:

depositing a seed layer inside the vias; and

electroplating to fill the vias and to extend electroplated material over the dielectric layer to define the p-type contact pad and the n-type contact pad.

18. The method as set forth in claim 16, wherein:

the disposing of electrical contact pads includes depositing a reflow layer; and

the flip-chip bonding of the contact pads to bonding bumps includes arranging the contact pads in contact with the bonding bumps and applying heat to the reflow layer to effect reflow bonding.

19. The method as set forth in claim 18, wherein the reflow layer includes tin and gold.

20. The method as set forth in claim 16, wherein the disposing of electrical contact pads over the vias and the dielectric layer includes:

filling the vias with a first conductive material;

disposing a second dielectric layer over the first conductive material, the second dielectric layer having vias passing therethrough for accessing the first conductive material; and

disposing the electrical contact pads over the second dielectric layer, the electrical contact pads electrically contacting the n-type and p-type electrodes through the first conductive material and the vias through the second dielectric layer.

21. The method as set forth in claim 20, wherein the disposing of electrical contact pads over the vias and the dielectric layer further includes:

prior to the disposing of the electrical contact pads, filling the vias through the second dielectric layer with a second conductive material and disposing a third dielectric layer over the second conductive material;

wherein the third dielectric layer has vias passing therethrough for accessing the second conductive material; and

wherein the electrical contact pads are disposed over the third dielectric layer and electrically contact the n-type and p-type electrodes through the first conductive material, the second conductive material, and the vias through the third dielectric layer.

22. The method as set forth in claim 16, wherein the light emitting diode further includes a portion of a substrate wafer that is shared with other light emitting diodes fabricated on the substrate wafer, the disposing of a dielectric layer and the disposing of electrical contact pads are performed as wafer-level processes that additionally dispose p-type and n-type electrical contact pads on the other light emitting diodes, and the method further includes:

after the disposing of the electrical contact pads and prior to the flip chip bonding, dicing the substrate wafer to separate the light emitting diode from the other light emitting diodes.

23. The method as set forth in claim 22, wherein the method further includes:

after the disposing of the electrical contact pads and prior to the dicing of the substrate wafer, performing at least additional wafer-level process to form at least one optical element on the light emitting diodes.

24. The method as set forth in claim 23, wherein the at least one optical element is selected from a group consisting of an encapsulant, a phosphor layer, and a reflective coating.

25. The method as set forth in claim 23, wherein the disposing a dielectric layer includes:

disposing the dielectric layer over the substrate wafer to seal front sides of the light emitting diodes including sealing the p-type and n-type electrical contact pads.

26. A method of processing a wafer having a plurality of light emitting diodes fabricated thereon, each light emitting diode having front-side n-type and p-type electrodes defining a minimum electrodes separation between the n-type and p-type electrodes, the method including:

disposing a dielectric layer over at least the n-type and p-type electrodes, the dielectric layer having vias passing therethrough for accessing the n-type and p-type electrodes;

disposing electrical contact pads over the vias and the dielectric layer, the electrical contact pads for each light emitting diode including a p-type contact pad that connects with the p-type electrode and an n-type contact pad that connects with the n-type electrode, the connecting being through the vias, the contact pads for each light emitting diode being arranged over the dielectric layer with a minimum contact pads separation between the p-type and n-type contact pads that is larger than the minimum electrodes separation between the n-type and p-type electrodes; and

after the disposing of the electrical contact pads, dicing the wafer to separate the light emitting diodes.

27. The method as set forth in claim 26, wherein the method further includes:

subsequent to the disposing of electrical contact pads and prior to the dicing of the wafer, applying at least one optical coating to a backside of the wafer opposite a side of the wafer on which the light emitting diodes are disposed.

28. The method as set forth in claim 26, wherein the dicing of the wafer includes making partial separation cuts through the wafer wherein the light emitting diodes remain secured together by the wafer, and breaking along the partial separation cuts to separate the light emitting diodes, the method further including:

after making the partial separation cuts and before breaking along the partial separation cuts, applying a metallic coating to surfaces formed by the partial separation cuts.

29. The method as set forth in claim 26, further including:

subsequent to the disposing of electrical contact pads and prior to the dicing, securing a front-side of the wafer to tape, the electrical contact pads being disposed on the front-side of the wafer;

subsequent to the dicing, stretching the tape to define a selected spacing of the separated light emitting diodes; and

subsequent to the stretching, applying a molding material to the light emitting diodes.

30. A method of flip chip bonding a light emitting diode to a printed circuit board without an interposed sub-mount, the method consisting essentially of the steps of:

forming one or more fanning layers on the front-side of the light emitting diode, each fanning layer including a dielectric layer and one or more metal layers, the topmost fanning layer defining electrical contact pads in electrical conimunication with front-side n-type and p-type electrodes of the light emitting diode, the electrical contact pads defining a minimum contact pads separation between the electrical contact pads in electrical communication with the n-type and p-type electrodes, respectively, that is larger than a minimum electrodes separation between the front-side n-type and p-type electrodes of the light emitting diode; and

flip-chip bonding the electrical contact pads to printed circuitry of the printed circuit board without an interposed sub-mount.

31. The method as set forth in claim 30, wherein the one or more fanning layers include at least two fanning layers.

32. The method as set forth in claim 30, wherein the one or more fanning layers seal the front-side n-type and p-type electrodes of the light emitting diode.