Method for four direction low capacitance ESD protection

• US 7,179,691 B1
• Filed: 07/29/2002
• Issued: 02/20/2007
• Est. Priority Date: 07/29/2002
• Status: Expired due to Term

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Chen, Shui Hun Yi, Lee, Jian-Hsing
• Primary Examiner(s): Hu; Shouxiang
• Application Number:
  US10/207,545
• Time in Patent Office: 1,667 Days
• Field of Search: 257355-363, 257/127, 257/170, 257/409, 257/605, 438/309, 438/585, 438/587, 438/588, 438/592, 438/140, 438/135
• US Class Current: 438/135
• CPC Class Codes: H01L 27/0255 using diodes as protective elements

Abstract

The invention describes a structure and a process for providing ESD semiconductor protection with reduced input capacitance. The structure consists of heavily doped P+ guard rings surrounding the I/O ESD protection device and the Vcc to Vss protection device. In addition, there is a heavily doped N+ guard ring surrounding the I/O protection device and its P+ guard ring. The guard rings enhance structure diode elements providing enhanced ESD energy discharge path capability enabling the elimination of a specific conventional Vss to I/O pad ESD protection device. This reduces the capacitance seen by the I/O circuit while still providing adequate ESD protection for the active circuit devices.

Claims

1. A method of forming a low input capacitance device structure on a P substrate for the purpose of providing four way electrostatic voltage discharge protection to an input/output (I/O) logic circuit line and including electrostatic discharge (ESD) protection to a power bus system, said power bus system comprising relatively-high and relatively-low power sources, the method comprising:

creating first and second N+ regions within said P substrate;

creating first and second P+ guard rings respectively surrounding said first and second N+ regions;

creating an N+ guard ring around said first N+ region and said first P+ guard ring; and

creating a electrical conductor system connecting said first N+ region to a pad, said first and second P+ guard rings to said relatively-low power source, and said N+ guard ring and said second N+ region to said relatively-high power source;

wherein there is no diode with two terminals respectively connected to said relatively-high power source and said pad, thereby eliminating a parasitic capacitor of said diode and providing a reduced capacitive load for said pad.

2. The method according to claim 1, further comprising:

creating a gate structure on the surface of said P substrate; and

creating N+ source and drain regions within said P substrate on either side of said gate structure forming a N-type field effect transistor (NFET) device;

wherein said first N+ region is said N+ drain region, and said electrical conductor system further connects said N+ source region and said gate structure to said relatively-low power source.

3. The method according to claim 1, further comprising:

creating a gate structure on the surface of said P substrate; and

creating N+ source and drain regions with said P substrate on either side of said gate structure forming a N-type field effect transistor (NFET) device;

wherein said second N+ region is said N+ drain region, and said electrical conductor system further connects said gate structure and said N+ source region to said relatively-low power source.

4. The method according to claim 3, further comprising:

creating an isolation structure within said substrate to separate said second P+ guard from said N+ guard ring.

5. The method according to claim 1, wherein said first N+ region is within an N-well surrounded by said first P+ guard ring, a P+ region is within said N-well, and said electrical conductor system connects said P+ region and said first N+ region to said pad.