Semiconductor device including metal insulator semiconductor field effect transistor and method of manufacturing the same

• US 7,179,702 B2
• Filed: 09/23/2005
• Issued: 02/20/2007
• Est. Priority Date: 11/06/2002
• Status: Expired due to Fees

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Matsuo, Kouji
• Primary Examiner(s): Lindsay, Jr.; Walter
• Assistant Examiner(s): Ahmadi; Mohsen
• Application Number:
  US11/232,861
• Publication Number:
  US 20060011989A1
• Time in Patent Office: 515 Days
• Field of Search: 438216-218, 438/385, 438/585, 438/197, 438/199, 438/158, 438/712, 438/800, 257/369, 257/407, 257/412, 257/410, 257/288, 257/364, 257/365, 257/374
• US Class Current: 438/216
• CPC Class Codes: H01L 21/28097 the final conductor layer next to the insulator being a metallic silicide
• CPC Class Codes: H01L 21/823814 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 21/823842 gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
• CPC Class Codes: H01L 21/823864 with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate

Abstract

A semiconductor device comprises a semiconductor substrate, an N-channel MISFET and a P-channel MISFET provided on the semiconductor substrate, each of the N- and P-channel MISFETs being isolated by an isolation region and having a gate insulating film, a first gate electrode film provided on the gate insulating film of the N-channel MISFET and composed of a first metal silicide, a second gate electrode film provided on the gate insulating film of the P-channel MISFET and composed of a second metal silicide made of a second metal material different from a first metal material composing the first metal silicide, and a work function of the first gate electrode film being lower than that of the second gate electrode film.

Claims

1. A method of manufacturing a semiconductor device, comprising:

forming an isolation region in a semiconductor substrate to provide an N- and a P-channel MISFET regions each surrounded by the isolation region;

forming an insulating film on the semiconductor substrate;

forming a conductive film on the insulating film;

patterning selectively the conductive film to provide a gate region in each of the MISFET regions;

forming source and drain regions in each of the MISFET regions for the patterned conductive film by a self-alignment way;

forming a sidewall insulating film around the patterned conductive film;

removing the conductive film and the insulating film of the gate region to provide a space region surrounded by the sidewall insulating film;

forming a gate insulating film on the N- and P-channel MISFET regions each surrounded by the space region, respectively;

forming a first metal silicide film on the gate insulating film within the space region to provide a first gate electrode film;

forming a metal film different from metal composing the first metal silicide film on the P-channel MISFET region; and

heat-treating the semiconductor substrate to form a second gate electrode film formed by a solid phase reaction between the first metal silicide film and the metal film, the second gate electrode film being composed of a second metal silicide made of a second metal material different from a first metal material composing the first metal silicide.

2. The method according to claim 1, wherein the second gate electrode film is formed by changing into a film including at least one material selected from the first metal material and a third metal silicide, the third metal silicide having the same constituent material of the first metal silicide and lower silicon content than the first metal silicide.

3. The method according to claim 1, wherein the number of silicon atoms per unit volume is 2.5 times more than the number of metal atoms per unit volume in a composition ratio between silicon and metal composing the first metal silicide.

4. The method according to claim 1, wherein the number of silicon atoms per unit volume is not more than the number of metal atoms per unit volume in the composition ratio between silicon and metal composing the third metal silicide.

5. The method according to claim 1, wherein a tungsten silicide film is formed as the first metal silicide.

6. The method according to claim 1, wherein the second metal silicide is composed of at least one kind of metal silicide selected from the metal suicides of platinum, palladium, and rhodium.

7. The method according to claim 1, wherein one material selected from the metal film and the metal silicide film is formed on the source and drain regions of the N- and P-channel MISFETs during a process for forming the sidewall insulating film and the space region.

8. The method according to claim 1, wherein a process for forming one material selected from the metal film and the metal silicide film on the source and drain regions of the N- and P-channel MISFETs is carried out after the heat treatment.