Device for minimizing differential pair length mismatch and impedance discontinuities in an integrated circuit package design

• US 7,180,011 B1
• Filed: 03/17/2006
• Issued: 02/20/2007
• Est. Priority Date: 03/17/2006
• Status: Active Grant

• Current Assignee: Bell Semiconductor, LLC (Hilco Inc. (d/b/a Hilco Global))
• Original Assignee: LSI Logic Corporation (Broadcom, Inc.)
• Inventors: Hall, Jeffrey, Nikoukary, Shawn
• Primary Examiner(s): Ngo; Hung V.
• Application Number:
  US11/276,938
• Time in Patent Office: 340 Days
• Field of Search: 174/520, 174/261, 174/255, 174/251, 174/257, 257/774, 257/776
• US Class Current: 174/520
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/16235 the bump connector connecting to a via metallisation of the item
• CPC Class Codes: H01L 23/49822 Multilayer substrates multilayer metallisation on monolayer substrate H01L23/498
• CPC Class Codes: H01L 23/49838 Geometry or layout
• CPC Class Codes: H01L 2924/15173 in a single layer of the multilayer substrate
• CPC Class Codes: H01L 2924/15174 in different layers of the multilayer substrate
• CPC Class Codes: H01L 2924/15311 being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/3011 Impedance
• CPC Class Codes: H01L 2924/3025 Electromagnetic shielding
• CPC Class Codes: H05K 1/0245 Lay-out of balanced signal pairs, e.g. differential lines or twisted lines
• CPC Class Codes: H05K 1/0248 Skew reduction or using delay lines
• CPC Class Codes: H05K 1/113 Via provided in pad; Pad over filled via
• CPC Class Codes: H05K 2201/09236 Parallel layout layout of balanced signal pairs H05K1/0245; superposed layout H05K2201/09672
• CPC Class Codes: H05K 2201/09263 Meander

Abstract

A method of routing an integrated circuit package design includes steps of receiving as input at least a portion of an integrated circuit design including a differential pair of two electrical conductors, calculating a value of length mismatch between the two electrical conductors, calculating an added trace length to compensate for an impedance discontinuity of a shorter one of the two electrical conductors, and extending the shorter one of the two electrical conductors by routing the added trace length entirely inside an area surrounded by a contact pad that electrically terminates the shorter one of the two electrical conductors. The routing for the differential pair with the added trace length is generated as output in the integrated circuit design.

Claims

1. An integrated circuit package comprises:

a differential pair of two electrical conductors; and

an added trace length that extends a shorter one of the two electrical conductors by routing the added trace length entirely inside an area surrounded by a contact pad that electrically terminates the shorter one of the two electrical conductors to compensate for an impedance discontinuity of the shorter one of the two electrical conductors.

2. The integrated circuit package of claim 1 further comprising an extension of the added trace length outside the area surrounded by the contact pad to compensate for a length mismatch between the two electrical conductors.

3. The integrated circuit package of claim 1 further comprising an adjustment of the added trace length to result in maximum signal symmetry for the differential pair.