Method of fabricating semiconductor device

• US 7,180,130 B2
• Filed: 09/24/2004
• Issued: 02/20/2007
• Est. Priority Date: 08/28/1997
• Status: Expired due to Fees

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Hitachi ULSI Systems Company Limited (Hitachi, Ltd.), Renesas Technology Corporation (Renesas Electronics Corporation)
• Inventors: Kubo, Sakae, Oishi, Kentaro, Kudo, Satoshi, Nakazawa, Yoshito, Shigematsu, Takashi, Uesawa, Kozo, Kobayashi, Masayoshi, Imai, Yasuo, Ohnishi, Akihiro, Numazawa, Sumito
• Primary Examiner(s): Kebede; Brook
• Assistant Examiner(s): GREEN, PHILLIP
• Application Number:
  US10/948,262
• Publication Number:
  US 20050037579A1
• Time in Patent Office: 879 Days
• Field of Search: 257/213, 257/288, 257/327, 257329-346, 438268-270
• US Class Current: 257/330
• CPC Class Codes: H01L 21/28114 characterised by the sectional shape, e.g. T, inverted-T
• CPC Class Codes: H01L 21/28185 with a treatment, e.g. annealing, after the formation of the gate insulator and before the formation of the definitive gate conductor
• CPC Class Codes: H01L 21/28194 by deposition, e.g. evaporation, ALD, CVD, sputtering, laser deposition H01L21/28202 takes precedence
• CPC Class Codes: H01L 21/28202 in a nitrogen-containing ambient, e.g. nitride deposition, growth, oxynitridation, NH3 nitridation, N2O oxidation, thermal nitridation, RTN, plasma nitridation, RPN
• CPC Class Codes: H01L 21/28211 in a gaseous ambient using an oxygen or a water vapour, e.g. RTO, possibly through a layer H01L21/28194 and H01L21/28202 take precedence
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/0869 Shape cell layout H01L29/0696
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/511 with a compositional variation, e.g. multilayer structures H01L29/516 takes precedence
• CPC Class Codes: H01L 29/513 the variation being perpendicular to the channel plane
• CPC Class Codes: H01L 29/518 the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material
• CPC Class Codes: H01L 29/66666 Vertical transistors H01L29/66712, H01L29/66742 take precedence
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence

Abstract

In a method of fabricating a semiconductor device having a MISFET of trench gate structure, a trench is formed from a major surface of a semiconductor layer of first conductivity type which serves as a drain region, in a depth direction of the semiconductor layer, a gate insulating film including a thermal oxide film and a deposited film is formed over the internal surface of the trench, and after a gate electrode has been formed in the trench, impurities are introduced into the semiconductor substrate of first conductivity type to form a semiconductor region of second conductivity type which serves as a channel forming region, and impurities are introduced into the semiconductor region of second conductivity type to form the semiconductor region of first conductivity type which serves as a source region.

Claims

1. A semiconductor device having a MISFETs forming region and a gate lead-out region on a main surface of a semiconductor substrate, comprising:

a plurality of first trenches in said semiconductor substrate in said MISFETS forming region;

a plurality of gate oxide films of said MISFETs formed in said plurality of first trenches;

a plurality of gate electrodes of said MISFETs formed on said plurality of gate oxide films;

a second trench formed in said gate lead-out region, said second trench being perpendicular to the first trenches;

a gate lead-out electrode formed in said second trench and outside the second trench in said gate lead-out region,

wherein said gate lead out region is located in a peripheral region of the main surface of said semiconductor substrate;

said gate lead-out electrode and gate electrodes are comprised of a same material;

said second trench is connected at an end portion of each of said first trenches;

said first trenches are terminated by said second trench; and

said plurality of gate electrodes are connected with said gate lead-out electrode.

2. A semiconductor device according to claim 1, wherein said MISFETs forming region is located on only one side of said gate lead-out region.

3. A semiconductor device according to claim 1, wherein said gate lead-out electrode and gate electrodes are comprised of a silicon film.

4. A semiconductor device according to claim 1, wherein said plurality of gate electrodes are electrically connected.

5. A semiconductor device according to claim 1, wherein a gate wiring is formed over said gate lead-out electrode, and

wherein said gate wiring electrode and gate lead-out electrode are electrically connected.

6. A semiconductor device according to claim 5, wherein a source electrode is formed over said plurality of gate electrodes, and

wherein said source electrode is electrically connected with source regions of said MISFETs, formed on the main surface of said semiconductor substrate.

7. A semiconductor device according to claim 6, wherein a drain electrode is formed on a back surface of said semiconductor substrate, and

wherein said drain electrode is electrically connected with a drain region of said MISFETs, formed in said semiconductor substrate.