Laser powered clock circuit with a substantially reduced clock skew

• US 7,180,379 B1
• Filed: 05/03/2004
• Issued: 02/20/2007
• Est. Priority Date: 05/03/2004
• Status: Active Grant

• Current Assignee: National Semiconductor Corporation (Texas Instruments, Inc.)
• Original Assignee: National Semiconductor Corporation (Texas Instruments, Inc.)
• Inventors: Vashchenko, Vladislav, Mirgorodski, Yuri, Hopper, Peter J., Lindorfer, Philipp
• Primary Examiner(s): Chang; Joseph
• Application Number:
  US10/838,485
• Time in Patent Office: 1,023 Days
• Field of Search: 331/66, 257/458
• US Class Current: 331/66
• CPC Class Codes: G06F 1/105 in which the distribution is at least partially optical

Abstract

A synchronous clock signal is generated in a large number of local clock circuits at the same time by exposing photoconductive regions in each local clock circuit to a pulsed light source that operates at a fixed frequency. The photoconductive regions generate photoconductive currents which are sufficient to cause a logic inverter to switch states.

Claims

1. A light powered clock system formed in a semiconductor material of a first conductivity type, the semiconductor material having a top surface, the light powered clock system comprising:

a local clock circuit including;

a first region of a second conductivity type that contacts the top surface of the semiconductor material, the first region including all contiguous regions of the second conductivity type;

a second region of the second conductivity type that contacts the top surface of the semiconductor material, the second region being spaced apart from the first region, and including all contiguous regions of the second conductivity type; and

a semiconductor region of the semiconductor material that lies between and contacts the first and second regions, the semiconductor region receiving light energy from a pulsed light source, the pulsed light source having a fixed frequency.

2. The light powered clock system of claim 1 wherein the local clock circuit further includes a current-to-voltage circuit electrically connected to the second region to generate a clock signal.

3. The light powered clock system of claim 2 wherein the current-to-voltage circuit includes:

a resistive element connected to the second region and ground;

a first inverter having an input connected the second region, and an output; and

a second inverter having an input connected to the output of the first inverter, and an output that generates the clock signal.

4. The light powered clock system of claim 1 and further comprising:

a transistor having;

a body of the first conductivity type;

a source region of the second conductivity type that contacts the body;

a drain region of the second conductivity type that contacts the body, the drain region being spaced apart from the source region;

a channel area located between the source and drain regions; and

a gate formed over and isolated from the channel area; and

an insulation region that contacts the first region, the second region, the source region, and the drain region, the channel area receiving no light energy from the pulsed light source.

5. The light powered clock system of claim 4 and further comprising a layer of metal formed over the insulation region, the layer of metal having a top surface and an opening that lies substantially vertically over the semiconductor region.

6. The light powered clock system of claim 1 wherein the pulsed light source includes a light emitting diode.

7. The light powered clock system of claim 1 and further comprising a plurality of regional clocking circuits, each regional clocking circuit and the local clock circuit being substantially identical.

8. A light powered clock system formed in a semiconductor material of a first conductivity type, the light powered clock system comprising:

a local clock circuit including;

a first region of a second conductivity type that contacts the semiconductor material;

a second region of the second conductivity type that contacts the semiconductor material, the second region being spaced apart from the first region; and

a semiconductor region of the semiconductor material that lies between and contacts the first and second regions, the semiconductor region receiving light energy from a pulsed light source, the pulsed light source having a fixed frequency, a current flowing from the first region to the second region through the semiconductor region only in response to the semiconductor region receiving light energy from the pulsed light source.

9. The light powered clock system of claim 8 wherein the local clock circuit further includes a current-to-voltage circuit electrically connected to the second region to generate a clock signal in response to the current.

10. The light powered clock system of claim 9 wherein the current-to-voltage circuit includes:

a resistive element connected to the second region and ground;

a first inverter having an input connected the second region, and an output; and

a second inverter having an input connected to the output of the first inverter, and an output that generates the clock signal.

11. The light powered clock system of claim 8 and further comprising:

a transistor having;

a body of the first conductivity type;

a source region of the second conductivity type that contacts the body;

a drain region of the second conductivity type that contacts the body, the drain region being spaced apart from the source region;

a channel area located between the source and drain regions; and

a gate formed over and isolated from the channel area; and

an insulation region that contacts the first region, the second region, the source region, and the drain region, the channel area receiving no light energy from the pulsed light source.

12. The light powered clock system of claim 11 and further comprising a layer of metal formed over the insulation region, the layer of metal having a top surface and an opening that lies substantially vertically over the semiconductor region.

13. The light powered clock system of claim 8 wherein the pulsed light source includes a light emitting diode.

14. The light powered clock system of claim 8 wherein the pulsed light source includes a light emitting diode and a lens structure.

15. The light powered clock system of claim 8 and further comprising a plurality of regional clocking circuits, each regional clocking circuit and the local clock circuit being substantially identical.

16. The light powered clock system of claim 8 wherein the local clock circuit further includes a gate formed over and isolated from the semiconductor region.

17. A method of generating a synchronous clock signal across an integrated circuit, the integrated circuit having:

a plurality of local clock circuits, each local clock circuit having;

a first region of a second conductivity type that contacts a semiconductor material of a first conductivity type;

a second region of the second conductivity type that contacts the semiconductor material, the second region being spaced apart from the first region; and

a semiconductor region of the semiconductor material that lies between and contacts the first and second regions, the semiconductor region receiving light energy from a light source,

the method comprising;

applying a voltage to the first region of each local clock circuit; and

pulsing the light source at a fixed frequency, a current flowing from the first region to the second region through the semiconductor region of each local clock circuit only in response to light energy from the pulsed light source.

18. The method of claim 17 wherein the integrated circuit further has:

a transistor having;

a body of the first conductivity type;

a source region of the second conductivity type that contacts the body;

a drain region of the second conductivity type that contacts the body, the drain region being spaced apart from the source region;

a channel area located between the source and drain regions; and

a gate formed over and isolated from the channel area; and

an insulation region that contacts the first region, the second region, the source region, and the drain region.

19. The method of claim 18 and further comprising protecting the channel area so that the channel area receives no light energy from the pulsed light source.

20. The method of claim 17 wherein:

the first region contacts a top surface of the semiconductor material, and includes all contiguous regions of the second conductivity type; and

the second region contacts the top surface of the semiconductor material, and includes all contiguous regions of the second conductivity type.