Apparatus and method for distributed memory control in a graphics processing system

• US 7,180,522 B2
• Filed: 08/31/2004
• Issued: 02/20/2007
• Est. Priority Date: 06/23/2000
• Status: Expired due to Fees

• Current Assignee: Round Rock Research LLC
• Original Assignee: Micron Technology, Inc.
• Inventors: Radke, William, Peterson, James R.
• Primary Examiner(s): Tung; Kee M.
• Assistant Examiner(s): NGUYEN, HAU H
• Application Number:
  US10/931,376
• Publication Number:
  US 20050030313A1
• Time in Patent Office: 903 Days
• Field of Search: 345/531, 345/532, 345536-538, 345/544, 345/564, 345/565, 710 22- 24, 711170-173
• US Class Current: 345/531
• CPC Class Codes: G06F 13/1657 Access to multiple memories
• CPC Class Codes: G09G 2360/121 using a cache memory
• CPC Class Codes: G09G 5/363 Graphics controllers
• CPC Class Codes: G09G 5/393 Arrangements for updating the contents of the bit-mapped memory

Abstract

A distributed memory controller memory system for a graphics processing system having addressable memory areas each coupled to a respective memory controller. The memory controllers are further coupled to each other through a memory controller bus upon which a memory access request and data may be passed from one memory controller to other memory controller. A memory access request to a memory location in one addressable memory area, but received by a memory controller coupled to another addressable memory area, is passed through the memory controller bus from the receiving memory controller to the memory controller coupled to the addressable memory area in which the requested location is located in order to service the memory access request. Additional memory controllers coupled to a respective addressable memory area may be included in the memory system. The memory controllers are coupled to the memory controller bus in order to receive and pass memory access requests from the other memory controllers.

Claims

1. A memory system, comprising:

a plurality of addressable memory areas;

a memory controller command bus configured to couple memory commands thereon; and

first, second and third memory controllers serially coupled to one another by the memory controller command bus and coupled to a respective one of the plurality of addressable memory areas, each memory controller configured to access the respective addressable memory area in response to receiving memory commands for accessing a memory location in the respective addressable memory area and further configured to forward memory commands for accessing a memory location in another one of the addressable memory areas to the memory controller coupled to the addressable memory area in which the memory location of the memory command is located.

2. The memory system of claim 1 wherein at least one of the plurality of memory controllers comprises a memory controller having registers for storing data defining a range of the first addressable memory area and the at least one memory controller is configured to compare a memory address corresponding to the memory location to the stored data to determine whether the memory location is in the respective addressable memory area.

3. The memory system of claim 2 wherein the registers are configured to store data representing a start address for the respective addressable memory area and a addressable memory size.

4. The memory system of claim 2 wherein the registers are configured to store data representing a start address for the respective addressable memory area and an end address for the first addressable memory area for the respective addressable memory area.

5. The memory system of claim 1 wherein at least one of the plurality of addressable memory areas comprises an addressable memory area of dynamic random access memory (“

DRAM”

) cells.

6. The memory system of claim 5 wherein the at least one of the plurality of addressable memory areas of DRAM cells comprises an addressable area of embedded memory of DRAM cells.

7. The memory system of claim 1 wherein at least one of the plurality of addressable memory areas comprises an addressable memory area for storing computer graphics data.

8. A computer system, comprising:

a system processor;

a memory interface circuit coupled to the system processor;

a system bus coupled to the memory interface circuit;

a graphics processing system coupled to the system bus; and

a system memory coupled to the memory interface circuit, the system memory comprising;

a plurality of addressable memory areas;

a memory controller command bus configured to couple memory commands thereon; and

first, second, and third memory controllers serially coupled to one another by the memory controller command bus and coupled to a respective one of the plurality of addressable memory areas, each memory controller configured to access the respective addressable memory area in response to receiving memory commands for accessing a memory location in the respective addressable memory area and further configured to forward memory commands for accessing a memory location in another one of the addressable memory areas to the memory controller coupled to the addressable memory area in which the memory location of the memory command is located.

9. The memory system of claim 8 wherein at least one of the plurality of memory controllers comprises a memory controller having registers for storing data defining a range of the first addressable memory area and the at least one memory controller is configured to compare a memory address corresponding to the memory location to the stored data to determine whether the memory location is in the respective addressable memory area.

10. The memory system of claim 9 wherein the registers are configured to store data representing a start address for the respective addressable memory area and a addressable memory size.

11. The memory system of claim 9 wherein the registers are configured to store data representing a start address for the respective addressable memory area and an end address for the first addressable memory area for the respective addressable memory area.

12. The memory system of claim 8 wherein at least one of the plurality of addressable memory areas comprises an addressable memory area of dynamic random access memory (“

DRAM”

) cells.

13. The memory system of claim 12 wherein the at least one of the plurality of addressable memory areas of DRAM cells comprises an addressable area of embedded memory of DRAM cells.

14. The memory system of claim 8 wherein at least one of the plurality of addressable memory areas comprises an addressable memory area for storing computer graphics data.

15. A method of accessing a memory location in a memory system having at least one addressable memory area, comprising:

receiving at a memory controller a memory access request to access the memory location;

determining whether the memory controller has access to the memory location;

in response to determining that the memory controller has access to the memory location, accessing the memory location;

in response to determining that the memory controller does not have access to the memory location, forwarding the memory access request to one of a plurality of memory controllers serially coupled to one another and to the memory controller that received the memory access request through a memory controller bus;

repeating the steps of receiving, determining, and forwarding until a target memory controller determines that it has access to the memory location; and

accessing the memory location through the target memory controller.

16. The method of claim 15 wherein determining whether the memory controller has access to the memory location comprises determining whether the memory location is located within an addressable memory area coupled to the respective memory controller.

17. The method of claim 16 wherein determining whether the memory location is located within an addressable memory area coupled to the respective memory controller comprises comparing a memory address corresponding to the memory location to data defining a range of addressable memory to which the respective memory controller has access.

18. The method of claim 17 wherein the comparing the memory address to data defining a range of addressable memory comprises comparing the memory address to first and second data defining a start address and addressable memory size, respectively, for the respective range of addressable memory.

19. The method of claim 17 wherein the comparing the memory address to data defining a range of addressable memory comprises comparing the memory address to first and second data defining a start address and an end address, respectively, for the respective range of addressable memory.