Data processing performance control based on a status signal indicating the maximum voltage that can be supported

• US 7,181,633 B2
• Filed: 11/19/2003
• Issued: 02/20/2007
• Est. Priority Date: 01/13/2003
• Status: Active Grant

• Current Assignee: Arm Ltd. (United Kingdom) (SoftBank Group Corp.)
• Original Assignee: Arm Ltd. (United Kingdom) (SoftBank Group Corp.)
• Inventors: Flynn, David Walter
• Primary Examiner(s): CRIBBS, MALCOLM
• Application Number:
  US10/715,410
• Publication Number:
  US 20040139361A1
• Time in Patent Office: 1,189 Days
• Field of Search: 713/300, 713/320, 713/322, 713/340
• US Class Current: 713/320
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 1/3237 by disabling clock generation or distribution
• CPC Class Codes: G06F 1/324 by lowering clock frequency
• CPC Class Codes: G06F 1/3296 by lowering the supply or operating voltage
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A data processing system includes a processor 46 operable to generate control signals to control one or more further circuits 4, 6 to adopt operational states to support different performance levels of the processor. The one or more further circuits generate current operation signals indicative of their current operation. Examples of further circuits are a clock generator 4 which generates a current operation signal indicative of a currently generated clock signal or possibly currently available clock signals. A voltage controller 6 may be a further circuit which serves to provide a power signal to the system and which generates a current operation signal indicative of the current maximum voltage level which the voltage controller is able to supply.

Claims

1. Apparatus for processing data, said apparatus comprising:

a processor operable to perform data processing operations, said processor being operable to generate a performance control signal indicative of a desired data processing performance level of said processor; and

one or more further circuits responsive to said performance control signal to operate so as to support said desired data processing performance level of said processor;

wherein

at least while responding to a change in said performance control signal, said one or more further circuits are operable to generate a current operation signal indicative of current operation of said one or more further circuits, wherein said one or more further circuits include a voltage controller operable to generate a power signal for said processor at a plurality of different voltage levels, said current operation signal being indicative of a maximum power supply voltage that can currently be supported by said voltage controller.

2. Apparatus as claimed in claim 1, wherein said one or more further circuits include a clock generator operable to generate a clock signal with a selectable clock frequency, said current operation signal being indicative of a clock frequency that is currently being generated by said clock generator.

3. Apparatus as claimed in claim 2, wherein said clock generator is operable to generate a clock signal with one or more permanently available clock signal frequencies and one or more selectively available clock signal frequencies.

4. Apparatus as claimed in claim 3, wherein a permanently enabled PLL circuit is operable to generate said one or more permanently available clock signal frequencies and a selectively enabled PLL circuit is operable to generate said one or more selectively available clock signal frequencies.

5. Apparatus as claimed in claim 1, wherein, in response to an increase in desired data processing performance level, said clock generator increases clock signal frequency when said voltage controller generates a current operation signal indicative of a generation of said power signal with a voltage level sufficient to support an increased clock signal frequency.

6. Apparatus as claimed in claim 1, wherein while responding to a change in performance control signal corresponding to a change from a first desired data processing performance level to a second desired data processing performance level, said one or more further circuits are operable to support data processing at at least one intermediate data processing performance level and said processor temporarily operates at said at least one intermediate data processing performance level during said change.

7. Apparatus as claimed in claim 6, wherein said one or more further circuits include a clock generator operable to generate a clock signal with a selectable clock frequency.

8. Apparatus as claimed in claim 7, wherein, in response to an increase in desired data processing performance level, said clock generator increases clock signal frequency to an intermediate clock signal frequency when a power signal is generated with a voltage level sufficient to support said intermediate clock signal frequency.

9. Apparatus as claimed in claim 6, wherein a priority signal serves to trigger said one or more further circuits change to support a maximum data processing performance level independently of said performance control signal.

10. A method of processing data, said method comprising the steps of:

performing data processing operations with a processor, said processor being operable to generate a performance control signal indicative of a desired data processing performance level of said processor; and

in response to said performance control signal, operating one or more further circuits so as to support said desired data processing performance level of said processor;

wherein

at least while responding to a change in said performance control signal, said one or more further circuits are operable to generate a current operation signal indicative of current operation of said one or more further circuit, wherein said one or more further circuit include a voltage controller operable to generate a power signal for said processor at a plurality of different voltage levels, said current operation signal being indicative of a maximum power supply voltage that can currently be supported by said voltage controller.

11. A method as claimed in claim 10, wherein said one or more further circuits include a clock generator operable to generate a clock signal with a selectable clock frequency, said current operation signal being indicative of a clock frequency that is currently being generated by said clock generator.

12. A method as claimed in claim 11, wherein said clock generator is operable to generate a clock signal with one or more permanently available clock signal frequencies and one or more selectively available clock signal frequencies.

13. A method as claimed in claim 12, wherein a permanently enabled PLL circuit is operable to generate said one or more permanently available clock signal frequencies and a selectively enabled PLL circuit is operable to generate said one or more selectively available clock signal frequencies.

14. A method as claimed in claim 10, wherein, in response to an increase in desired data processing performance level, said clock generator increases clock signal frequency when said voltage controller generates a current operation signal indicative of a generation of said power signal with a voltage level sufficient to support an increased clock signal frequency.

15. A method as claimed in claim 10, wherein while responding to a change in performance control signal corresponding to a change from a first desired data processing performance level to a second desired data processing performance level, said further circuit is operable to support data processing at at least one intermediate data processing performance level and said processor temporarily operates at said at least one intermediate data processing performance level during said change.

16. A method as claimed in claim 15, wherein said one or more further circuits include a clock generator operable to generate a clock signal with a selectable clock frequency.

17. A method as claimed in claim 16, wherein, in response to an increase in desired data processing performance level, said clock generator increases clock signal frequency to an intermediate clock signal frequency when a power signal is generated with a voltage level sufficient to support said intermediate clock signal frequency.

18. A method as claimed in claim 15, wherein a priority signal serves to trigger said further circuit change to support a maximum data processing performance level independently of said performance control signal.