Wireless no-touch testing of integrated circuits

• US 7,181,663 B2
• Filed: 03/01/2004
• Issued: 02/20/2007
• Est. Priority Date: 03/01/2004
• Status: Active Grant

• Current Assignee: Advantest Corporation
• Original Assignee: Verigy Limited (Advantest Corporation)
• Inventors: Hildebrant, Andrew S.
• Primary Examiner(s): TU, CHRISTINE TRINH LE
• Application Number:
  US10/790,906
• Publication Number:
  US 20050193294A1
• Time in Patent Office: 1,086 Days
• Field of Search: None
• US Class Current: 714/726
• CPC Class Codes: G01R 31/2886 Features relating to contacting the IC under test, e.g. probe heads; chucks G01R31/2865 takes precedence, test connections, e.g. test sockets, or probes per se, G01R1/04 or G01R1/06
• CPC Class Codes: G01R 31/3025 Wireless interface with the DUT
• CPC Class Codes: G01R 31/318572 Input/Output interfaces
• CPC Class Codes: G01R 31/31905 Interface with the device under test [DUT], e.g. arrangements between the test head and the DUT, mechanical aspects, fixture
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A wireless integrated circuit test method and system is presented. The invention allows testing of one or more integrated circuits configured with a wireless interface and a test access mechanism which controls input of test data received over a wireless connection from a test station to test structures which test functional blocks on the integrated circuit. Via the wireless connection, multiple integrated circuits or similarly equipped devices under test can be tested simultaneously. The invention also enables concurrent testing of independently testable functional blocks on any given integrated circuit under test.

Claims

1. An integrated circuit comprising:

one or more functional blocks to be tested when said integrated circuit is placed in a test mode;

one or more test structures configured to test said one or more functional blocks when said integrated circuit is placed in said test mode;

a wireless interface which receives test data over a wireless connection, the test data comprising a frame having a plurality of bits; and

a test access mechanism which controls input of said received test data to said test structures, wherein at least two of said plurality of bits of the frame are applied to different respective test structures on said integrated circuit.

2. An integrated circuit in accordance with claim 1, wherein:

said wireless interface implements an Internet Protocol stack which extracts test data from, and transmits test results over, said wireless connection in formatted frames.

3. An integrated circuit in accordance with claim 1, wherein:

said test structures comprise one or more scan chains; and

said test access mechanism comprises a scan chain loading mechanism.

4. An integrated circuit in accordance with claim 3, wherein:

said scan chain loading mechanism simultaneously loads a plurality of scan chains with different bits of the frame of said test data.

5. An integrated circuit in accordance with claim 3, wherein:

the different bits of the frame are loaded into the one or more scan chains in parallel.

6. A system for testing an integrated circuit, comprising:

a plurality of integrated circuits, each comprising;

one or more functional blocks to be tested when said integrated circuit is placed in a test mode;

one or more test structures configured to test said one or more functional blocks when said integrated circuit is placed in said test mode;

a wireless interface which receives and extracts test data from a wireless connection; and

a test access mechanism which controls input of said received test data to said test structures; and

a test station comprising a test station wireless interface which simultaneously transmits the test data over the wireless connection to the wireless interfaces of each of the plurality of integrated circuits.

7. A system in accordance with claim 6, wherein:

each of the wireless interfaces of the plurality of integrated circuits implements an Internet Protocol stack which extracts test data from, and transmits test results over, said wireless connection in formatted frames.

8. A system in accordance with claim 7, wherein:

said test data comprises a frame having a plurality of bits at least two of which are driven to respective different test structures on said respective one or more integrated circuits.

9. A system in accordance with claim 6, wherein:

said test structures on said respective plurality of integrated circuits comprise one or more scan chains; and

said test access mechanism on said respective plurality of integrated circuits comprises a scan chain loading mechanism.

10. A system in accordance with claim 9, wherein:

said scan chain loading mechanism on each of said respective plurality of integrated circuits simultaneously loads a plurality of scan chains.

11. A system in accordance with claim 9, wherein:

said scan chain loading mechanism on each of said respective plurality of integrated circuits loads one or more scan chains in parallel.

12. A method for testing integrated circuits comprising:

obtaining test data;

simultaneously sending said test data via a wireless interface over a wireless connection to a plurality of integrated circuit devices under test, each comprising one or more functional blocks to be tested when said respective integrated circuit device under test is placed in a test mode, one or more test structures configured to test said one or more functional blocks when said respective integrated circuit device under test is placed in said test mode, a wireless interface which receives and extracts said test data from said wireless connection; and

a test access mechanism which controls input of said received test data to said test structures of said respective integrated circuit device under test.

13. A method in accordance with claim 12, comprising:

receiving test results via said wireless interface from said wireless connection from said plurality of integrated circuit devices under test, said test results returned from said one or more test structures of said respective plurality of integrated circuit devices under test from application of said test data to said one or more functional blocks of said respective pl of integrated circuit devices under test.