Prioritizing of nets for coupled noise analysis

• US 7,181,711 B2
• Filed: 04/27/2005
• Issued: 02/20/2007
• Est. Priority Date: 04/27/2005
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Foreman, Eric A., Habitz, Peter A., Schaeffer, Gregory M.
• Primary Examiner(s): DO, THUAN V
• Application Number:
  US10/908,101
• Publication Number:
  US 20060248485A1
• Time in Patent Office: 664 Days
• Field of Search: 716/2, 716/6, 716/12
• US Class Current: 716/113
• CPC Class Codes: G06F 30/3312 Timing analysis

Abstract

A system and method of performing microelectronic chip timing analysis, wherein the method comprises identifying failing timing paths in a chip; prioritizing the failing timing paths in the chip according to a size of random noise events occurring in each timing path; attributing a slack credit statistic for all but highest order random noise events occurring in each timing path; and calculating a worst case timing path scenario based on the prioritized failing timing paths and the slack credit statistic. Preferably, the random noise events comprise non-clock events. Moreover, the random noise events may comprise victim/aggressor net groups belonging to different regularity groups. Preferably, the size of random noise events comprises coupled noise delta delays due to the random noise events occurring in the chip.

Claims

1. A method of performing microelectronic chip timing analysis, said method comprising:

identifying failing timing paths in a chip;

prioritizing said failing timing paths in said chip according to a size of random noise events occurring in each timing path, wherein said prioritizing of said failing timing paths in said chip comprises sorting a timing impact of random noise events occurring in said chip by an occurrence of an event and a probability that said event will occur;

attributing a timing value for all random noise events occurring in each timing path except for a statistically determined number of the largest random noise events occurring in each timing path;

calculating a worst case timing path in said chin based on the prioritized failing timing paths and said timing value; and

correcting only a portion of said chip comprising said worst cast timing path.

2. The method of claim 1, wherein said random noise events comprise non-clock events.

3. The method of claim 1, wherein said random noise events comprise victim/aggressor net groups belonging to different regularity groups.

4. The method of claim 1, wherein said size of random noise events comprises coupled noise delta delays due to said random noise events occurring in said chip.

5. The method of claim 1, wherein said statistically determined number indicates the number of random data nets in said chip that can switch simultaneously.

6. The method of claim 1, wherein said prioritizing of said failing timing paths in said chip comprises:

calculating a time delay change for each victim net influenced by at least one aggressor net connected to said victim net through at least one coupling capacitor;

analyzing a netlist of said chip by grouping logically similar timing paths together; and

performing a timing run to identify positive slack nets and negative slack nets.

7. The method of claim 6, wherein said calculating of said worst case timing path comprises determining whether grouped victim nets and aggressor nets are switching in a same clock cycle.

8. A program storage device readable by computer, tangibly embodying a program of instructions executable by said computer to perform a method of performing microelectronic chip timing analysis, said method comprising:

identifying failing timing paths in a chip;

prioritizing said failing timing paths in said chip according to a size of random noise events occurring in each timing path, wherein said prioritizing of said failing timing paths in said chip comprises sorting a timing impact of random noise events occurring in said chip by an occurrence of an event and a probability that said event will occur;

attributing a timing value for all random noise events occurring in each timing path except for a statistically determined number of the largest random noise events occurring in each timing path;

calculating a worst case timing path in said chip based on the prioritized failing timing paths and said timing value; and

correcting only a portion of said chip comprising said worst cast timing path.

9. The program storage device of claim 8, wherein said random noise events comprise non-clock events.

10. The program storage device of claim 8, wherein said random noise events comprise victim/aggressor net groups belonging to different regularity groups.

11. The program storage device of claim 8, wherein said size of random noise events comprises coupled noise delta delays due to said random noise events occurring in said chip.

12. The program storage device of claim 8, wherein in said method, said statistically determined number indicates the number of random data nets in said chip that can switch simultaneously.

13. The program storage device of claim 8, wherein in said method, said prioritizing of said failing timing paths in said chip comprises:

calculating a time delay change for each victim net influenced by at least one aggressor net connected to said victim net through at least one coupling capacitor;

analyzing a netlist of said chip by grouping logically similar timing paths together; and

performing a timing run to identify positive slack nets and negative slack nets.

14. The program storage device of claim 13, wherein in said method, said calculating of said worst case timing path comprises determining whether grouped victim nets and aggressor nets are switching in a same clock cycle.

15. A system for performing microelectronic chip timing analysis, said system comprising:

a simulator adapted to identify failing timing paths in a chip;

a processor connected to said simulator, said processor being adapted to;

prioritize said failing timing paths in said chip according to a size of random noise events occurring in each timing path, and

sort a timing impact of said random noise events occurring in said chip by an occurrence of an event and a probability that said event will occur;

an analyzer connected to said processor, said analyzer being adapted to attribute a timing value for all random noise events occurring in each timing path except for a statistically determined number of the largest random noise events occuring in each timing path;

a calculator connected to said processor and said analyzer, said calculator being adapted to calculate a worst case timing path in said chip based on the prioritized failing timing paths and said timing value, wherein said worst case timing path indicates the portion of said chip to be corrected.

16. The system of claim 15, wherein said random noise events comprise non-clock events and victim/aggressor net groups belonging to different regularity groups.

17. The system of claim 15, wherein said size of random noise events comprises coupled noise delta delays due to said random noise events occurring in said chip.

18. The system of claim 15, wherein said statistically determined number indicates the number of random data nets in said chip that can switch simultaneously.

19. The system of claim 15, wherein said processor is further adapted to:

calculate a time delay change for each victim net influenced by at least one aggressor net connected to said victim net through at least one coupling capacitor;

analyze a netlist of said chip by grouping logically similar timing paths together; and

perform a timing run to identify positive slack nets and negative slack nets.

20. The system of claim 19, wherein said calculator is further adapted to determine whether grouped victim nets and aggressor nets are switching in a same clock cycle.