Structure and manufacturing process of a nano device transistor for a biosensor

• US 7,182,914 B2
• Filed: 11/26/2003
• Issued: 02/27/2007
• Est. Priority Date: 08/26/2003
• Status: Active Grant

• Current Assignee: Industrial Technology Research Institute
• Original Assignee: Industrial Technology Research Institute
• Inventors: Kao, Ming-Jer, Wang, Hung-Hsiang, Wei, Jeng-Hua, Lai, Ming-Jiunn, Chen, Hsin-Hui
• Primary Examiner(s): Le; Long V.
• Assistant Examiner(s): LUM, LEON YUN BON
• Application Number:
  US10/721,876
• Publication Number:
  US 20050045875A1
• Time in Patent Office: 1,189 Days
• Field of Search: 435/4, 435/6, 435/7.1, 4352871-2872, 435/287.9, 435/288.3, 436/518, 436/524, 436/149, 422/50, 422/68.1, 422/82.01, 422/82.02, 257/27, 257/253, 257/288, 324/769, 327/203, 327/206, 327/208, 327/389
• US Class Current: 422/82.01
• CPC Class Codes: B82Y 15/00 Nanotechnology for interacting, sensing or actuating, e.g. quantum dots as markers in protein assays or molecular motors
• CPC Class Codes: B82Y 5/00 Nanobiotechnology or nanomedicine, e.g. protein engineering or drug delivery
• CPC Class Codes: G01N 27/4146 involving nanosized elements, e.g. nanotubes, nanowires
• CPC Class Codes: H10K 10/466 Lateral bottom-gate IGFETs comprising only a single gate
• CPC Class Codes: H10K 19/10 comprising field-effect transistors

Abstract

The present invention relates to a structure and manufacturing process of a nano device transistor for a biosensor. The structure, the manufacturing process and the related circuit for a carbon nano tube or nano wire transistor biosensor device are provided. The refurbished nano device is used for absorbing various anti-bodies so as to detect the specific antigens or absorbing various biotins. Therefore, the object of the present invention to detect the specific species for bio measurement can be achieved.

Claims

1. A structure of a nano device transistor for a biosensor, comprising:

a silicon substrate having SiO₂ deposited thereon;

a bottom gate positioned on the silicon substrate having SiO₂ deposited thereon;

a gate dielectric layer positioned on the bottom gate being an interface layer for insulating the bottom gate;

a nano channel layer positioned on the gate dielectric layer;

a drain positioned extending over a first portion of a top surface of the nano channel layer and a first portion of a top surface of the gate dielectric layer;

a source positioned extending over a second portion of the top surface of the nano channel layer and a second portion of the top surface of the gate dielectric layer;

a ceiling gate dielectric layer comprising a first ceiling gate dielectric layer portion and a second ceiling gate dielectric layer portion positioned on the drain and the source, respectively;

a ceiling gate positioned on the ceiling gate dielectric layer;

a first protection layer positioned on the first ceiling gate dielectric layer portion; and

a second protection layer positioned on the second ceiling gate dielectric layer portion.

2. The structure of claim 1, wherein the bottom gate comprises metal or poly-silicon.

3. The structure of claim 1, wherein a surfactant and a target anti-body are absorbable on the nano channel layer.

4. The structure of claim 1, wherein the drain and the source are metal electrodes.

5. The structure of claim 1, wherein the first protection layer and the second protection layer comprise silicon oxide, silicon nitride or other insulation materials.

6. The structure of claim 1, wherein the gate dielectric layer comprises silicon oxide, silicon nitride or other gate dielectric materials.

7. The structure of claim 1, wherein the ceiling gate comprises metal.

8. The structure of claim 1, wherein the first ceiling gate dielectric layer portion and the second ceiling gate dielectric layer portion comprise silicon oxide, silicon nitride or other insulation materials.

9. The structure of claim 1, wherein the ceiling gate covers a portion of the nano channel layer.

10. The structure of claim 1, wherein a plurality of the nano device transistors are connected to form a serial connection structure of the nano device transistors.

11. The structure of claim 1, wherein a plurality of the nano channel layers are connected between the drain and the source in the nano device transistor, or a plurality of the nano device transistors are connected to form a parallel connection structure for the nano device transistor.

12. The structure of claim 1, wherein the first protection layer, the second protection layer and the nano channel layer are used for defining a detection area.