Silicon-on-insulator wafer transfer method using surface activation plasma immersion ion implantation for wafer-to-wafer adhesion enhancement

• US 7,183,177 B2
• Filed: 11/16/2004
• Issued: 02/27/2007
• Est. Priority Date: 08/11/2000
• Status: Expired due to Fees

• Current Assignee: Applied Materials Incorporated
• Original Assignee: Applied Materials Incorporated
• Inventors: Ramaswamy, Kartik, Hanawa, Hiroji, Collins, Kenneth S., Nguyen, Andrew, Al-Bayati, Amir, Gallo, Biagio
• Primary Examiner(s): SARKAR, ASOK K
• Application Number:
  US10/989,993
• Publication Number:
  US 20050070073A1
• Time in Patent Office: 833 Days
• Field of Search: 438/455, 438/458
• US Class Current: 438/458
• CPC Class Codes: C23C 14/48 Ion implantation
• CPC Class Codes: C23C 16/507 using external electrodes, e.g. in tunnel type reactors
• CPC Class Codes: H01J 37/32082 Radio frequency generated discharge H01J37/32357, H01J37/32366, H01J37/32394 and H01J37/32403 take precedence
• CPC Class Codes: H01J 37/321 the radio frequency energy being inductively coupled to the plasma
• CPC Class Codes: H01J 37/32357 Generation remote from the workpiece, e.g. down-stream
• CPC Class Codes: H01J 37/32412 Plasma immersion ion implantation
• CPC Class Codes: H01L 21/2236 from or into a plasma phase
• CPC Class Codes: H01L 21/26513 of electrically active species
• CPC Class Codes: H01L 21/31604 Deposition from a gas or vapour H01L21/31691, H01L21/31695 take precedence
• CPC Class Codes: H01L 21/318 composed of nitrides
• CPC Class Codes: H01L 21/76254 with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823814 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 21/823842 gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
• CPC Class Codes: H01L 29/6659 with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET

Abstract

A method of fabricating a semiconductor-on-insulator structure from a pair of semiconductor wafers, includes forming an oxide layer on at least a first surface of a first one of the wafers and performing a bonding enhancement implantation step by ion implantation of a first species in the first surface of at least either of the pair of wafers. The method further includes performing a cleavage ion implantation step on one of the pair of wafers by ion implanting a second species to define a cleavage plane across a diameter of the wafer at the predetermined depth below the top surface of the one wafer. The wafers are then bonded together by placing the first surfaces of the pair of wafers onto one another so as to form an semiconductor-on-insulator structure. The method also includes separating the one wafer along the cleavage plane so as to remove a portion of the one wafer between the second surface and the cleavage plane, whereby to form an exposed cleaved surface of a remaining portion of the one wafer on the semiconductor-on-insulator structure. Finally, the cleaved surface is smoothed, preferably by carrying out a low energy high momentum ion implantation step.

Claims

1. A method of fabricating a semiconductor-on-insulator structure from a pair of semiconductor wafers, each of said wafers having opposing first and second surfaces, said method comprising:

forming an oxide layer on at least a first surface of a first one of said wafers;

performing a cleavage ion implantation step on one of said pair of wafers by ion implanting a second species to define a cleavage plane across a diameter of said wafer at a predetermined depth below the top surface of said one wafer;

performing a bonding enhancement implantation step by ion implantation of a first species in the first surface of at least either of said pair of wafers;

bonding said pair of wafers together by placing the first surfaces of said pair of wafers onto one another so as to form an semiconductor-on-insulator structure;

separating said one wafer along said cleavage plane so as to remove a portion of said one wafer between said second surface and said cleavage plane, whereby to form an exposed cleaved surface of a remaining portion of said one wafer on said semiconductor-on-insulator structure;

smoothing said cleaved surface;

wherein said bonding enhancement implantation step comprises plasma immersion ion implantation of said first species; and

wherein the step of plasma immersion ion implantation of said first species comprises;

placing either of said pair of wafers in a first process zone;

introducing a first process gas containing a precursor of said first species;

generating a first oscillating plasma current from said first process gas in a first closed torroidal path extending through a first reentrant conduit external of said first process zone and through said first process zone.

2. The method of claim 1 wherein the step of plasma immersion ion implantation further comprises:

generating a second oscillating plasma current from said first process gas in a second closed torroidal path separate from and transverse to said first torroidal path and extending through a second reentrant conduit external of said first process zone and through said first process zone, said first and second closed torroidal paths intersecting in said first process zone.

3. The method of claim 2 wherein:

said first process zone is defined between the wafer therein and a first overlying ceiling; and

the step of introducing a first process gas comprises injecting the first process gas into said first process zone through said ceiling.

4. The method of claim 1 further comprising attracting ions from said plasma current to the top surface of the wafer in the process zone with an ion energy corresponding to an implant depth profile peaking at or near the top surface of the wafer in the process zone.

5. The method of claim 4 wherein the step of attracting ions comprises coupling plasma bias power to the wafer in the process zone to produce a plasma sheath voltage at the top surface thereof corresponding to said implant depth profile.

6. The method of claim 5 wherein the step of coupling plasma bias power comprises coupling a pulsed D.C. voltage waveform to the wafer.

7. The method of claim 1 wherein said first species comprises oxygen.

8. The method of claim 1 wherein said first species comprises one of nitrogen, hydrogen, silicon, germanium.

9. The method of claim 1 wherein said cleavage implantation step comprises plasma immersion ion implantation of said second species.

10. The method of claim 9 wherein the step of plasma immersion ion implantation of said second species comprises:

placing said one wafer in a second process zone;

introducing a second process gas containing a precursor of said second species;

generating a third oscillating plasma current from said second process gas in a third closed torroidal path extending through a third reentrant conduit external of said second process zone and through said second process zone.

11. The method of claim 10 wherein the step of plasma immersion ion implantation further comprises:

generating a fourth oscillating plasma current from said second process gas in a fourth closed torroidal path separate from and transverse to said third torroidal path and extending through a third reentrant conduit external of said second process zone and through said second process zone, said third and fourth closed torroidal paths intersecting in said second process zone.

12. The method of claim 10 wherein:

said second process zone is defined between said one wafer and a second overlying ceiling; and

the step of introducing a second process gas comprises injecting the second process gas into the second process zone through the second ceiling.

13. The method of claim 10 further comprising attracting ions from the plasma current to the top surface of said one wafer with an ion energy corresponding to an implant depth profile peaking at said cleavage plane.

14. The method of claim 13 wherein the step of attracting ions comprises coupling plasma bias power to said one wafer to produce a plasma sheath voltage at the top surface of said one wafer corresponding to the implant depth profile peaking at said cleavage plane.

15. The method of claim 14 wherein the step of coupling plasma bias power comprises coupling a pulsed D.C. voltage waveform to the wafer.

16. The method of claim 9 wherein said smoothing step comprises plasma immersion ion implantation of a third species into said cleaved surface.

17. The method of claim 16 wherein the step of plasma immersion ion implantation of said third species comprises:

placing said semiconductor-on-insulator structure in a third process zone;

introducing a third process gas containing a precursor of said third species;

generating a fifth oscillating plasma current from said third process gas in a fifth closed torroidal path extending through a fifth reentrant conduit external of said third process zone and through said third process zone.

18. The method of claim 17 wherein the step of plasma immersion ion implantation of said third species further comprises:

generating a sixth oscillating plasma current from said third process gas in a sixth closed torroidal path separate from and transverse to said fifth torroidal path and extending through a sixth reentrant conduit external of said third process zone and through said third process zone, said fifth and sixth closed torroidal paths intersecting in said third process zone.

19. The method of claim 17 wherein:

said third process zone is defined between said semiconductor-on-insulator structure and a third overlying ceiling; and

the step of introducing a third process gas comprises injecting the third process gas into said third process zone through said third ceiling.

20. The method of claim 17 further comprising attracting ions from said plasma current to said cleaved top surface of the semiconductor-on-insulator structure with an ion energy corresponding to an implant depth profile peaking at or near said cleaved surface.

21. The method of claim 20 wherein the step of attracting ions comprises coupling plasma bias power to the semiconductoron-insulator structure to produce a plasma sheath voltage at the top surface thereof corresponding to the implant depth profile peaking at the cleaved surface.

22. The method of claim 21 wherein the step of coupling plasma bias power comprises coupling a pulsed D.C. voltage waveform to the semiconductor-on-insulator structure.

23. The method of claim 17 wherein said third species comprises a relatively heavy species.

24. The method of claim 23 wherein said third species comprises one of xenon, argon, nitrogen, silicon, germanium.

25. The method of claim 1 wherein said second species comprises hydrogen.

26. The method of claim 1 further comprising:

prior to the step of bonding said pair of wafers together, performing a defect removal step on either or both said pair of wafers, comprising;

optically detecting locations of defects including contamination in the top surface of the wafer; and

ablating said defects by directing a laser beam to said locations.

27. The method of claim 1 wherein a bonding enhancement implantation step is performed on the top surface of each of said pair of wafers.