Super trench MOSFET including buried source electrode and method of fabricating the same

• US 7,183,610 B2
• Filed: 04/30/2004
• Issued: 02/27/2007
• Est. Priority Date: 04/30/2004
• Status: Expired due to Fees

• Current Assignee: Siliconix Incorporated (Vishay Intertechnology Incorporated)
• Original Assignee: Siliconix Incorporated (Vishay Intertechnology Incorporated)
• Inventors: Shi, Sharon, Terrill, Kyle, Chen, Kuo-In, Lui, Kam Hong, Pattanayak, Deva N., Xu, Robert, Yue, Christiana, Bai, Yuming
• Primary Examiner(s): Dickey; Thomas L.
• Application Number:
  US10/836,833
• Publication Number:
  US 20050242392A1
• Time in Patent Office: 1,033 Days
• Field of Search: 257/E29.262, 257/E29.263, 257330-333
• US Class Current: 257/333
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/41741 for vertical or pseudo-vertical devices
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

In a trench MOSFET, the lower portion of the trench contains a buried source electrode, which is insulated from the epitaxial layer and semiconductor substrate but in electrical contact with the source region. When the MOSFET is in an “off” condition, the bias of the buried source electrode causes the “drift” region of the mesa to become depleted, enhancing the ability of the MOSFET to block current. The doping concentration of the drift region can therefore be increased, reducing the on-resistance of the MOSFET. The buried source electrode also reduces the gate-to-drain capacitance of the MOSFET, improving the ability of the MOSFET to operate at high frequencies. The substrate may advantageously include a plurality of annular trenches separated by annular mesas and a gate metal layer that extends outward from a central region in a plurality of gate metal legs separated by source metal regions.

Claims

1. A trench-gated transistor formed in a semiconductor die, said transistor comprising:

an arrangement of annular trenches in the die, each of said trenches being separated from an adjacent trench by an annular mesa, said trenches comprising a gate electrode, said die comprising a doped region;

a source metal layer and a gate metal layer, said source metal layer being in electrical contact with said doped region, said gate metal layer being in electrical contact with said gate electrode, said gate metal layer comprising a plurality of gate metal legs that extend radially outward from a central area toward a perimeter of said die, said source metal layer comprising a plurality of sections located between said gate metal legs.

2. The trench-gated transistor of claim 1 wherein each of said trenches is in the shape of a square annulus.

3. The trench-gated transistor of claim 1 wherein each of said trenches is in the shape of a square annulus with rounded corners.

4. The trench-gated transistor of claim 3 wherein said transistor comprises four gate metal legs, each of said gate metal legs extending towards a corner of said die.

5. The trench-gated transistor of claim 1 wherein each of said trenches is in the shape of a circular ring.

6. The trench-gated transistor of claim 1 wherein each of said trenches is in the shape of a rectangular annulus.

7. The trench-gated transistor of claim 1 wherein each of said trenches is in the shape of a rectangular annulus with rounded corners.

8. The trench-gated transistor of claim 1 wherein each of said trenches is in the shape of a hexagonal annulus.

9. The trench-gated transistor of claim 1 wherein the transistor is a MOSFET, said MOSFET comprising:

a source region of a first conductivity type located adjacent at least one of said trenches at a first surface of said die, said source metal layer overlying said first surface of said die and being in electrical contact with said source region;

a body region of a second conductivity type opposite to said first conductivity type adjacent said at least one trench and forming a junction with said source region;

a drift region of said first conductivity type located adjacent said at least one trench and forming a junction with said body region; and

a drain region of said first conductivity type adjacent a second surface of said die opposite to said first surface;

said at least one trench comprising

an upper portion comprising a gate electrode, said gate electrode being separated from said body region by a gate dielectric layer; and

a lower portion comprising a buried source electrode, said buried source electrode being electrically isolated from said drift region by a second dielectric layer and from said gate electrode by a third dielectric layer, said buried source electrode being electrically connected to said source metal layer.

10. The trench-gated transistor of claim 9 comprising a peripheral trench, said peripheral trench being deeper than a trench located radially inward from said peripheral trench, said peripheral trench being lined with a fourth dielectric layer and containing a conductive material, said conductive material in said peripheral trench being electrically connected to said source metal layer.

11. The trench-gated transistor of claim 10 wherein said peripheral trench is wider than said trench radially inward from said peripheral trench.

12. The trench-gated transistor of claim 10 wherein at least one additional trench is deeper than said trench located radially inward from said peripheral trench.

13. The trench-gated transistor of claim 9 wherein a width of said at least one trench, a width of a mesa adjacent said at least one trench, and a doping concentration in said drift region are established such that said drift region is fully depleted at a drain-to-source voltage equal to Vds but is not fully depleted at a drain-to-source voltage of less than Vds, said voltage Vds being approximately equal to 10⁷ times a thickness of said second dielectric layer in cm.

14. The trench-gated transistor of claim 9 wherein said third oxide layer wraps around an upper portion of said buried source electrode so as to create a vertical overlap between said gate electrode and said buried source electrode.

15. The trench-gated transistor of claim 1 wherein the transistor is a MOSFET, said MOSFET comprising:

a source region of a first conductivity type located adjacent at least one of said trenches at a first surface of said die, said source metal layer overlying said first surface of said die and being in electrical contact with said source region;

a body region of a second conductivity type opposite to said first conductivity type adjacent said at least one trench and forming a junction with said source region; and

a drain region of said first conductivity type adjacent a second surface of said die opposite to said first surface.

16. The trench-gated transistor of claim 13 further comprising a drift region of said first conductivity type located adjacent said at least one trench and forming a junction with said body region.

17. The trench-gated transistor of claim 1 wherein the transistor is a MOSFET, said MOSFET comprising:

a source region of a first conductivity type located adjacent at least one of said trenches at a first surface of said die;

a body region of a second conductivity type opposite to said first conductivity type adjacent said at least one trench and forming a junction with said source region;

a drift region of said first conductivity type located adjacent said at least one trench and forming a junction with said body region;

a drain region of said first conductivity type adjacent a second surface of said die opposite to said first surface; and

said source metal layer overlying said first surface of said die and being in electrical contact with said source region;

said at least one trench comprising

a source electrode in electrical contact with said source metal layer;

a thick oxide layer lining the floor and lower portions of the sidewalls of said at least one trench;

a multilayer structure lining the upper portions of the sidewalls of said at least one trench, said multilayer structure comprising a first thin oxide layer in contact with said substrate, a second thin oxide layer in contact with said source electrode, and a polysilicon layer separating said first and second thin oxide layers.

18. The trench-gated transistor of claim 17 wherein said multilayer structure extends downward to a level below said junction between said body region and said drift region.

19. The trench-gated MOSFET of claim 17 wherein a thickness of said multilayer structure is approximately the same as a thickness of said thick oxide layer.

20. The trench-gated MOSFET of claim 17 wherein said polysilicon layer comprises said gate electrode.

21. The trench-gated transistor of claim 1 wherein said gate legs are positioned radially at selected angular intervals around said central area of said die.

22. The trench-gated transistor of claim 1 wherein said plurality of gate legs comprises at least four gate legs extending radially outward from said central area toward said perimeter of said die.