Wireless radio frequency technique design and method for testing of integrated circuits and wafers

• US 7,183,788 B2
• Filed: 03/01/2004
• Issued: 02/27/2007
• Est. Priority Date: 05/15/2000
• Status: Expired due to Fees

• Current Assignee: Scanimetrics, Inc.
• Original Assignee: Scanimetrics, Inc.
• Inventors: Moore, Brian
• Primary Examiner(s): TANG, MINH NHUT
• Application Number:
  US10/788,491
• Publication Number:
  US 20040164760A1
• Time in Patent Office: 1,093 Days
• Field of Search: 324/765, 324/763, 324/754, 324/158.1, 327/161, 327/269, 327/261, 327/262, 254/8, 254/4
• US Class Current: 324/754.31
• CPC Class Codes: G01R 31/2831 Testing of materials or semi-finished products, e.g. semiconductor wafers or substrates G01R31/318511 takes precedence; testing during manufacture H01L22/00
• CPC Class Codes: G01R 31/2884 using dedicated test connectors, test elements or test circuits on the IC under test G01R31/2855 takes precedence
• CPC Class Codes: G01R 31/3025 Wireless interface with the DUT
• CPC Class Codes: G01R 31/303 of integrated circuits G01R31/305 - G01R31/315 take precedence
• CPC Class Codes: H01L 22/34 Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line switching, multiplexing, gating devices G01R19/25; process control with lithography, e.g. dose control, G03F7/20; structures for alignment control by optical means G03F7/70633
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/3011 Impedance

Abstract

The present invention is for an apparatus and method for the wireless testing of Integrated Circuits and wafers. The apparatus comprises a test unit external from the wafer and at least one test circuit which is fabricated on the wafer which contains the Integrated Circuit. The test unit transmits an RF signal to power the test circuit. The test circuit, comprising a variable ring oscillator, performs a series of parametric tests at the normal operating frequency of the Integrated Circuit and transmits the test results to the test unit for analysis.

Claims

1. A test circuit for testing an integrated circuit on a wafer, the test circuit formed on the wafer with the integrated circuit, the test circuit comprising:

a) a variable ring oscillator circuit including;

i) a base ring oscillator circuit;

ii) a plurality of sub-circuits selectively coupled to the base ring oscillator circuit; and

,

iii) a plurality of switching elements for selectively coupling at least one of the plurality of sub-circuits to the base ring oscillator circuit; and

,

b) a control circuit to enable at least one of the plurality of switching elements to selectively couple at least one of the sub-circuits to the base ring oscillator circuit to produce different versions of the variable ring oscillator circuit,

the test circuit conducts a separate test of the integrated circuit for at least one of the versions of the variable ring oscillator circuit.

2. The test circuit of claim 1 wherein each test conducted by the test circuit is a parametric test.

3. The test circuit of claim 2 wherein the sub-circuits when coupled to the base ring oscillator circuit change the frequency of oscillation of the variable ring oscillator circuit.

4. The test circuit of claim 3 wherein at least one sub-circuit comprises a capacitive load to change the frequency of oscillation of the variable ring oscillator circuit.

5. The test circuit of claim 4 wherein the capacitive load comprises at least one capacitor.

6. The test circuit of claim 3 wherein at least one sub-circuit comprises a capacitive load and a resistive load to change the frequency of oscillation of the variable ring oscillator circuit.

7. The test circuit of claim 6 wherein at least one sub circuit comprises a delay element to change the frequency of oscillation of the variable ring oscillator circuit.

8. The test circuit of claim 7 wherein the delay element comprises at least one inverter.

9. The test circuit of claim 8 wherein each inverter is a standard CMOS inverter.

10. The test circuit of claim 6 wherein the capacitive load comprises at least one capacitor and the resistive load comprises at least one resistor.

11. The test circuit of claim 1 wherein the control circuit comprises a sequencer to selectively couple the sub-circuits to the variable ring oscillator circuit to produce a series of test states.

12. The test circuit of claim 11 wherein the control circuit further comprises a second ring oscillator adapted to provide a first clock signal, and a divider coupled to the second ring oscillator and the sequencer and adapted to provide a second clock signal, wherein the second clock signal is provided to the sequencer so that the sequencer can provide a series of test state signals to the variable ring oscillator circuit and plurality of sub-circuits.

13. The test circuit of claim 1 wherein the test circuit is formed on the wafer with at least two metallization layers of the integrated circuit.

14. The test circuit of claim 1 wherein the test circuit is formed on the wafer with at least one metallization layer and one polysilicon layer of the integrated circuit.

15. The test circuit of claim 1 wherein the test circuit produces a test result signal that is the output of the variable ring oscillator circuit.

16. The test circuit of claim 1 wherein the test circuit is formed adjacent to a die containing the integrated circuit.

17. The test circuit of claim 1 wherein the test circuit is formed on a die that contains the integrated circuit.

18. The test circuit of claim 1 wherein the test circuit is formed on a large percentage of dies on the wafer.

19. The test circuit of claim 1 wherein the test circuit is formed on dies near the edge of the wafer.