Direct application voltage variable material, devices employing same and methods of manufacturing such devices

• US 7,183,891 B2
• Filed: 10/05/2004
• Issued: 02/27/2007
• Est. Priority Date: 04/08/2002
• Status: Active Grant

• Current Assignee: Littelfuse Incorporated
• Original Assignee: Littelfuse Incorporated
• Inventors: Vyas, Tushar, Harris, Edwin James, Pachla, Timothy, Colby, James A.
• Primary Examiner(s): HOANG, TU BA
• Application Number:
  US10/958,442
• Publication Number:
  US 20050057867A1
• Time in Patent Office: 875 Days
• Field of Search: 338/20, 338/21, 338/22.SD, 338/67, 338/204, 338307-309, 338/312, 338/314, 296/23, 298/25, 361/111, 361/137, 257536-538
• US Class Current: 338/21
• CPC Class Codes: H01C 7/12 Overvoltage protection resistors series resistors structurally associated with spark gaps H01T1/16
• CPC Class Codes: H01G 2/14 Protection against electric or thermal overload by cooling H01G2/08
• CPC Class Codes: H02H 9/044 Physical layout, materials not provided for elsewhere varistors H01C7/12; spark-gaps H01T; Ovshinsky devices H10N70/00
• CPC Class Codes: H05K 1/0257 Overvoltage protection
• CPC Class Codes: H05K 1/0259 Electrostatic discharge [ESD] protection
• CPC Class Codes: H05K 1/0298 Multilayer circuits
• CPC Class Codes: H05K 1/0393 Flexible materials H05K1/038 takes precedence; specific organic compositions are classified in H05K1/0313 and subgroups
• CPC Class Codes: H05K 1/167 incorporating printed resistors
• CPC Class Codes: H05K 2201/0738 Use of voltage responsive materials, e.g. voltage switchable dielectric or varistor materials
• CPC Class Codes: H05K 2201/09763 Printed component having superposed conductors, but integrated in one circuit layer
• CPC Class Codes: H05K 3/28 Applying non-metallic protective coatings H05K3/0091 takes precedence; methods for intermediate insulating layers for build-up multilayer circuits H05K3/4673

Abstract

A voltage variable material (“VVM”) including an insulative binder that is formulated to intrinsically adhere to conductive and non-conductive surfaces is provided. The binder and thus the VVM is self-curable and applicable in a spreadable form that dries before use. The binder eliminates the need to place the VVM in a separate device or to provide separate printed circuit board pads on which to electrically connect the VVM. The binder and thus the VVM can be directly applied to many different types of substrates, such as a rigid FR-4 laminate, a polyimide, a polymer or a multilayer PCB via a process such as screen or stencil printing. In one embodiment, the VVM includes two types of conductive particles, one with a core and one without a core. The VVM can also have core-shell type semiconductive particles.

Claims

1. A circuit carrier comprising:

a first insulating layer;

a second insulating layer;

first and second electrodes positioned between the first and second insulating layers and separated from each other by a gap, wherein at least one of the electrodes is provided on one of the first and second insulating layers; and

a voltage variable material (“

VVM”

) that protects against an electrostatic discharge (“

ESD”

) event, the VVM located in the gap between the first and second insulating layers and contacting the first and second electrodes, wherein at least one of the insulating layers has a minimum thickness for preventing energy from the ESD event from traveling across the thickness that is determined by and greater than or equal to (i) an ESD magnitude rating divided by (ii) a dielectric strength of the at least one insulating layer.

2. The circuit carrier of claim 1, wherein the VVM is provided so that it is substantially flush with the first and second electrodes.

3. The circuit carrier of claim 1, wherein at least one of the first and second insulating layers is made of a material selected from the group consisting of:

FR-4, epoxy resin, ceramic, resin coated foil, teflon, polyimide and glass.

4. The circuit carrier of claim 1, wherein the first electrode is a signal conductor and the second electrode is a ground/shield conductor.

5. The circuit carrier of claim 1, which includes a plurality of first electrodes that are signal conductors, the second electrode being a ground/shield conductor, and a plurality of gaps between the first electrodes and the second electrode, and wherein the VVM is located in the gaps between the first and second insulating layers and contacts the first electrodes and the second electrode.

6. The circuit carrier of claim 1, wherein the gap is a first gap and which includes third and fourth electrodes positioned between the first and second insulating layers and separated from each other by a second gap, and wherein the VVM is located in the second gap and contacts the third and fourth electrodes.

7. The circuit carrier of claim 6, wherein the first and third electrodes are signal electrodes and the second and fourth electrodes are ground/shield electrodes.

8. The circuit carrier of claim 1, wherein the first and second conductors are electrodes of a high-definition multimedia (“

HDMI”

) interface, a universal serial bus (“

USB”

) interface or a firewire interface.

9. The circuit carrier of claim 8, which is located in a connector housing of the the HDMI, USB or firewire interface.

10. The circuit carrier of claim 1, which includes at least one third electrode located on a side of at least one of the first and second insulating layers that is opposite the VVM and the first and second electrodes.

11. The circuit carrier of claim 10, which includes (i) at least one fourth electrode creating at least one gap with the third electrode located on said opposite side and (ii) VVM located in the gap between the third and fourth electrodes, the VVM contacting the third and fourth electrodes.

12. The circuit carrier of claim 11, which includes at least one additional insulating layer covering the third and fourth electrodes and the VVM placed in the gap between the third and fourth electrodes.

13. The circuit carrier of claim 1, which is (i) small enough to be placed inside of a surface mountable component or (ii) large enough to hold a connector that connects the circuit carrie to a mating unit.

14. The circuit carrier of claim 1, wherein the VVM includes an insulating binder that has at least one characteristic selected from the group consisting of being:

(i) self-adhering and (ii) self-curing.

15. The circuit carrier of claim 1, wherein the VVM includes an insulating binder, (i) semiconductive particles with a doped core and a shell located about the core held in the binder and (ii) conductive particles held in the binder.

16. The circuit carrier of claim 1, wherein the VVM includes an insulating binder, (i) semiconductive particles held in the binder and (ii) conductive particles consisting essentially of a single material held in the binder.

17. The circuit carrier of claim 1, wherein the VVM includes an insulating binder, (i) first conductive particles that include a conductive core and a shell located about the core held in the binder and (ii) second conductive particles each comprising a substantially pure material held in the binder.

18. The circuit carrier of claim 1, wherein the VVM includes an insulating binder, (i) first conductive particles held in the binder that include a conductive core and a shell located about the conductive core, (ii) second conductive particles each comprising a substantially pure material held in the binder and (iii) particles with a semiconductive core and a shell located about the semiconductive core held in the binder.

19. The circuit carrier of claim 1, wherein the VVM is applied in the gap via a process selected from the group consisting of:

(i) stencil printing with trimming, (ii) stencil printing without trimming, (iii) screen printing with trimming, (iv) screen printing without trimming, (v) controlled dispensing with trimming, (vi) controlled dispensing without trimming, (vii) pick and place dispensing with trimming and (viii) pick and place dispensing without trimming.

20. A method of manufacturing a circuit carrier comprising the steps of:

(a) providing a first electrode on a first insulating layer;

(b) providing a second electrode on the first insulation layer and spacing the first and second electrodes apart to form a gap between the electrodes;

(c) screen printing/stenciling a layer of voltage variable material (“

VVM”

) that protects against an electrostatic discharge event into the gap so as to contact the first and second electrodes; and

(d) providing a second insulating layer over at least a portion of the electrodes and the VVM so that the second insulating layer has a minimum thickness for preventing energy from the electrostatic discharge event from traveling across the thickness that is greater than or equal to (i) an electrostatic discharge (“

ESD”

) magnitude rating divided by (ii) a dielectric strength of the second insulating layer.

21. The method of claim 20, which includes screen printing/stenciling the VVM into the gap so that the VVM is flush with the first and second electrodes without trimming the VVM after the screen printing/stenciling step.

22. The method of claim 20, which includes the step of trimming the VVM so that the VVM is flush with the first and second electrodes.

23. The method of claim 20, which includes repeating steps (a) to (d) where the second insulating layer becomes the first insulating layer of repeated steps (a) and (b) and a third insulating layer is applied in repeated step (d).

24. A method of manufacturing a circuit carrier comprising the steps of:

(a) providing a first electrode on a first insulating layer;

(b) providing a second electrode on the first insulation layer and spacing the first and second electrodes apart to form a gap between the electrodes;

(c) using an apparatus that holds and stores voltage variable material (“

VVM”

) that protects against an electrostatic discharge event under pressure to dispense the VVM into the gap so as to contact the first and second electrodes; and

(d) providing a second insulating layer over at least a portion of the electrodes and the VVM so that the second insulating layer has a minimum thickness for preventing energy from the electrostatic discharge event from traveling across the thickness that is greater than or equal to (i) an electrostatic discharge (“

ESD”

) magnitude rating of the VVM divided by (ii) a dielectric strength of the second insulating layer.

25. The method of claim 24, which includes using the apparatus to apply the VVM into the gap so that the VVM is flush with the first and second electrodes without trimming the VVM after the screen printing step.

26. The method of claim 24, which includes the step of trimming the VVM so that the VVM is flush with the first and second electrodes.

27. The method of claim 24, which includes repeating steps (a) to (d) where the second insulating layer becomes the first insulating layer of repeated steps (a) and (b) and a third insulating layer is applied in repeated step (d).

28. The method of claim 24, wherein the apparatus mechanically pressurizes the VVM, pneumatically pressurizes the VVM or atomizes the VVM.

29. The method of claim 24, which includes moving the apparatus in at least one direction to dispense the VVM to a desired location on the first insulating layer.

30. The method of claim 24, which includes moving the apparatus in at least one direction to dispense the VVM continuously to form a trace of VVM on the first insulating layer.