Sub-ranging digital to analog converter for radiofrequency amplification

• US 7,183,958 B2
• Filed: 09/08/2004
• Issued: 02/27/2007
• Est. Priority Date: 09/08/2004
• Status: Expired due to Fees

• Current Assignee: Pine Valley Investments, Inc. (L3Harris Technologies, Inc.)
• Original Assignee: M/A-Com Eurotec BV (TE Connectivity Limited)
• Inventors: Quilligan, Gerard T., Heaney, Eugene P., Nagle, Pierce J.
• Primary Examiner(s): Jeanglaude; Jean Bruner
• Application Number:
  US10/935,952
• Publication Number:
  US 20060049971A1
• Time in Patent Office: 902 Days
• Field of Search: 341/144, 341/145, 341/141, 341/118, 341/136, 341/153, 600/547, 315/364, 345/98
• US Class Current: 341/144
• CPC Class Codes: H03M 1/68 with conversions of different sensitivity, i.e. one conversion relating to the more significant digital bits and another conversion to the less significant bits
• CPC Class Codes: H03M 1/745 with weighted currents

Abstract

An apparatus and method for amplifying a radiofrequency signal using a main Digital to Analog Converter (RFDAC) and a subordinate Digital to Analog Converter (Sub-DAC). The main RFDAC provides a first portion of a N-bit digital output, which specifies the amplification level of the radiofrequency signal, and the sub-DAC provides a second portion of the N-bit digital word. Together, the main RFDAC and the Sub-DAC convert a complete N-bit digital word, where N specifies the resolution of the output radiofrequency signal.

Claims

1. A circuit comprising:

a first digital to analog converter for providing amplification of a signal based on a digital control word; and

,

a second digital to analog converter,

wherein a first plurality of bits representing the most significant bits of the digital control word are supplied to the first digital to analog converter, and a second plurality of bits representing the least significant bits of the digital control word are supplied to the second digital to analog converter, and

wherein the second digital to analog converter supplies an analog representation of the second plurality of bits to the first digital to analog converter.

2. The circuit of claim 1, wherein the first digital to analog converter includes a signal processor for receiving the first plurality of bits and the analog representation of the second plurality of bits.

3. The circuit of claim 2, wherein the signal processor includes M output bit lines, such that each bit of the first plurality of bits are separately provided on M−

1 of the output bit lines, and a composite signal representing the second plurality of bits is provided on the remaining output bit line.

4. The circuit of claim 1, wherein the first plurality of bits and the second plurality of bits are combined in the first digital to analog converter to form the digital control word.

5. A method for amplifying a signal, comprising the steps of:

generating a first plurality of bit values representative of the most significant bits of a digital signal;

generating a second plurality of bit values representative of the least significant bits of the digital signal;

converting the second plurality of bit values into a first analog signal; and

,

generating a second analog signal based on the first analog signal and the first plurality of bit values.

6. The method of claim 5, further comprising:

combining the first and second pluralities of bit values to form a digital control word;

wherein the digital control word is comprised of N bits, where N is equal to the number of bits in the first plurality of bits plus the number of bits in the second plurality of bits.

7. The method of claim 6, wherein the first analog signal represents a single bit of the digital word.

8. A circuit comprising:

a digital processing circuit coupled to an input terminal for converting an analog signal into at least two digital signals, at least one of said digital signals comprising an amplitude signal, and at least one of said digital signals comprising a phase signal; and

,

a digital to analog circuit including;

a first digital to analog converter, said first digital to analog converter controlled by a most significant digital word; and

a second digital to analog converter, said second digital to analog converter controlled by a least significant digital word,

wherein an output of the second digital to analog converter is combined with the most significant digital word to form a composite output.

9. A circuit comprising:

a first digital to analog converter for providing amplification of a signal based on a digital control word; and

,

a second digital to analog converter,

wherein a first plurality of bits representing the most significant bits of the digital control word are supplied to the first digital to analog converter, and a second plurality of bits representing the least significant bits of the digital control word are supplied to the second digital to analog converter;

wherein the second digital to analog converter supplies an analog representation of the second plurality of bits to the first digital to analog converter; and

wherein an output voltage of the circuit is defined by the following equation;

V_out=(V_RF*CC)/2^C+(V_RF*CF)/2<sup>(C+F−

1)</sup>,

where V_out=output voltage, V_RF=voltage of the signal to be amplified, CC=Most Significant Bit (MSB) binary code input to the first digital to analog converter, C=Most Significant Bit (MSB) resolution of the first digital to analog converter, CF=Least Significant Bit (LSB) binary code input to the second digital to analog converter, and F=Least Significant Bit (LSB) resolution of the second digital to analog converter.

10. A circuit comprising:

a first digital to analog converter, said first digital to analog converter controlled by a most significant digital word; and

a second digital to analog converter, said second digital to analog converter controlled by a least significant digital word,

wherein an output of the second digital to analog converter is applied to a least significant bit input of the first digital to analog converter, so that the output of the first digital to analog converter is finely controlled by the least significant digital word and coarsely controlled by the most significant digital word.

11. A circuit comprising:

a first digital to analog converter, said first digital to analog converter controlled by a most significant digital word; and

a second digital to analog converter, said second digital to analog converter controlled by a least significant digital word,

wherein an output of the second digital to analog converter is combined with the most significant digital word to form a composite output digital word.

12. A circuit comprising:

a digital processing circuit coupled to an input terminal for converting an analog signal into at least two digital signals, at least one of said digital signals comprising an amplitude signal, and at least one of said digital signals comprising a phase signal; and

,

a digital to analog circuit for applying an N-bit digital word to the phase signal, said digital to analog circuit comprising a first digital to analog converter and a second digital to analog converter, wherein a first plurality of bits representative of the most significant bits of the N-bit digital word are supplied to the first digital to analog converter, and wherein a second plurality of bits representative of the least significant bits of the N-bit digital word are supplied to the second digital to analog converter, and wherein the second digital to analog converter supplies an analog representation of the second plurality of bits of the N-bit digital word to the first digital to analog converter.