Parallel electrode memory

• US 7,184,289 B2
• Filed: 11/12/2003
• Issued: 02/27/2007
• Est. Priority Date: 11/12/2003
• Status: Expired due to Fees

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Coulson, Richard L., Andideh, Ebrahim
• Primary Examiner(s): HUR, JUNG H
• Application Number:
  US10/712,205
• Publication Number:
  US 20050099878A1
• Time in Patent Office: 1,203 Days
• Field of Search: 365/51, 365/63, 365/65, 365/145, 365/130, 365/163, 365/117, 365/113, 365/109
• US Class Current: 365/51
• CPC Class Codes: G11C 11/22 using ferroelectric elements
• CPC Class Codes: G11C 5/063 Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay

Abstract

A series of address lines extend in a first direction through at least two layers of memory material spaced apart in the first direction. The memory material may be a ferroelectric polymer in one embodiment. The arrangement of lines and layers may increase the density of a memory in one embodiment.

Claims

1. A memory comprising:

a first layer and a second layer of memory material spaced from one another in a first direction; and

a first address line and a second address line extending substantially in said first direction through said first and second layers.

2. The memory of claim 1 wherein said memory material includes a ferroelcctric polymer material.

3. The memory of claim 1 including third and fourth address lines which extend in a second direction different from said first direction.

4. The memory of claim 3 wherein said first and second directions are substantially transverse to one another.

5. The memory of claim 3 wherein said third and fourth address lines are in said first layer.

6. The memory of claim 5 including a first cell formed in said first layer between said first and third address lines and a second cell formed in said first layer between said second and fourth address lines.

7. The memory of claim 6 wherein a bicell of two cells is formed in said first layer on opposed sides of said third address line.

8. The memory of claim 7 wherein said bicell is formed between said first and second address lines, and wherein said bicell includes said third address line.

9. The memory of claim 1 having more than two lines.

10. The memory of claim 1 having more than two layers.

11. The memory of claim 1 wherein said layers are vertically stacked.

12. The memory of claim 11 wherein successive layers are spaced by an insulator.

13. The memory of claim 1 wherein said lines are vias extending vertically, said memory including a substrate having a surface, said first direction being substantially transverse to said surface.

14. A method comprising:

forming a first and a second layer of memory material, said first and second layers spaced in a first direction; and

forming a first and a second address line extending substantially in said first direction through said first and second layers.

15. The method of claim 14 including forming a third and fourth address line extending substantially transversely to said first direction.

16. The method of claim 15 including forming said third and fourth address lines in said first layer.

17. The method of claim 14 including forming a bicell structure.

18. The method of claim 14 wherein forming a first and second layer of memory material includes forming ferroelectric polymer memory material layers.

19. The method of claim 14 including forming more than two lines and more than two layers.

20. The method of claim 14 including forming said lines by forming metal filled vias.

21. The method of claim 14 including forming an insulator between said first and second layers.

22. A method comprising:

addressing a polymer memory using first lines extending substantially in a first direction to address cells defined in at least two layers of memory material spaced from one another in said first direction, said lines extending through said at least two layers.

23. The method of claim 22 including using second lines extending substantially transversely to said first direction to address cells between said first and second lines.

24. The method of claim 23 including addressing a bicell between a second line and two adjacent first lines.

25. The method of claim 23 including addressing a cell in one layer by applying a potential to adjacent first and second lines.

26. The method of claim 22 wherein addressing includes addressing a ferroelectric polymer memory.

27. A system comprising:

a controller;

a wireless interface coupled to said controller; and

a polymer memory coupled to said controller, said memory including a substrate having an upper surface, a plurality of first address lines extending in a first direction, at least two layers of memory material spaced from one another in said first direction, said lines extending through said at least two layers.

28. The system of claim 27 including third and fourth address lines extending substantially transversely to the first direction.

29. The system of claim 28 wherein said lines form a bicell structure.

30. The system of claim 29 wherein said interface includes a dipole antenna.

31. The system of claim 27 having more than two lines.

32. The system of claim 27 wherein said polymer memory is a ferroelectric polymer memory.

33. The memory of claim 27 having more than two layers.

34. The memory of claim 27 wherein said layers are vertically stacked.

35. The memory of claim 34 wherein successive layers are spaced by an insulating layer.

36. The memory of claim 27 wherein said lines are vias extending vertically, said substrate having an upper surface, said first direction being substantially transverse to said surface.