Logic process DRAM

• US 7,184,290 B1
• Filed: 05/27/2005
• Issued: 02/27/2007
• Est. Priority Date: 06/28/2000
• Status: Expired due to Fees

• Current Assignee: Marvell International Limited (Marvell Technology Group Limited)
• Original Assignee: Marvell International Limited (Marvell Technology Group Limited)
• Inventors: Lee, Winston, Sutardja, Sehat, Lee, Peter
• Primary Examiner(s): Nguyen; Viet Q.
• Application Number:
  US11/138,681
• Time in Patent Office: 641 Days
• Field of Search: 365/63, 365/72, 365/189.02, 365/230.02, 365/51
• US Class Current: 365/63
• CPC Class Codes: G11C 11/4094 Bit-line management or control circuits
• CPC Class Codes: G11C 11/4097 Bit-line organisation, e.g. bit-line layout, folded bit lines
• CPC Class Codes: G11C 5/063 Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
• CPC Class Codes: G11C 7/02 with means for avoiding parasitic signals
• CPC Class Codes: G11C 7/12 Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
• CPC Class Codes: G11C 7/18 Bit line organisation; Bit line lay-out
• CPC Class Codes: H10B 12/482 Bit lines

Abstract

A dynamic random access memory (DRAM) unit includes pluralities of bit line pairs and word lines. Each bit line pair includes first and second bit lines aligned with each other in an end-to-end arrangement. The first bit lines are arranged substantially parallel and consecutively adjacent to one another. The second bit lines are arranged substantially parallel and consecutively adjacent to one another. Each word line is associated with either the first bit lines or the second bit lines. A first array is formed by the first bit lines and the associated word lines. A second array is formed by the second bit lines and the associated word lines. Each of a plurality of memory cells is associated with every other bit line along each word line. Each of a plurality of multiplexers is in communication with two adjacent bits lines within one of the first and second arrays.

Claims

1. A semiconductor integrated circuit device, including a dynamic random access memory (DRAM) unit, the DRAM unit comprising:

a plurality of bit line pairs,

wherein each bit line pair includes a first bit line and a second bit line,

wherein the first bit line and the second bit line within each bit line pair are aligned with each other in an end-to-end arrangement,

wherein the first bit lines are arranged substantially parallel and consecutively adjacent to one another,

wherein the second bit lines are arranged substantially parallel and consecutively adjacent to one another;

a plurality of word lines,

wherein each word line is associated with one of the first bit lines and the second bit lines such that a first array is formed by the first bit lines and the associated word lines and a second array is formed by the second bit lines and the associated word lines;

a plurality of memory cells,

wherein each of the plurality of memory cells is associated with every other bit line along each word line; and

a first plurality of multiplexers,

wherein each of the first plurality of multiplexers is in communication with two adjacent bits lines within one of the first and second arrays, wherein said first array acts as a sense array and said second array acts as a reference array for said first array when at least one of said plurality of word lines is active in said first array.

2. The semiconductor integrated circuit device of claim 1, wherein, for each word line, each bit line that is not associated with the plurality of memory cells acts as a shield between bit lines that are associated with the plurality of memory cells.

3. The semiconductor integrated circuit device of claim 1, wherein the DRAM unit comprises:

a plurality of sense amplifiers,

wherein each of the plurality of sense amplifiers is in communication with a multiplexer associated with two adjacent first bit lines of the first array and a multiplexer associated with two corresponding adjacent second bit lines of the second array.

4. The semiconductor integrated circuit device of claim 1, wherein the DRAM unit comprises:

a second plurality of multiplexers in communication with a voltage source input and with two adjacent bit lines within one of the first and second arrays.

6. The semiconductor integrated circuit device of claim 1, wherein the DRAM unit comprises:

a first interconnect layer; and

a second interconnect layer,

wherein each bit line is associated with both the first and second interconnect layers.

7. The semiconductor integrated circuit device of claim 6, wherein the first interconnect layer comprises a first metal layer and the second interconnect layer comprises a second metal layer.

8. The semiconductor integrated circuit device of claim 6, wherein the first interconnect layer comprises a metal layer and the second interconnect layer comprises a polysilicon layer.

9. The semiconductor integrated circuit device of claim 6, wherein the first interconnect layer comprises a polysilicon layer and the second interconnect layer comprises a metal layer.

10. The semiconductor integrated circuit device of claim 1, wherein the DRAM unit is manufactured using a logic process.

11. The semiconductor integrated circuit device of claim 1, wherein the DRAM unit is manufactured using a DRAM process.

5. A semiconductor integrated circuit device, including a dynamic random access memory (DRAM) unit, the DRAM unit comprising:

a plurality of bit line pairs,

wherein each bit line pair includes a first bit line and a second bit line,

wherein the first bit line and the second bit line within each bit line pair are aligned with each other in an end-to-end arrangement,

wherein the first bit lines are arranged substantially parallel and consecutively adjacent to one another,

wherein the second bit lines are arranged substantially parallel and consecutively adjacent to one another;

a plurality of word lines,

wherein each word line is associated with one of the first bit lines and the second bit lines such that a first array is formed by the first bit lines and the associated word lines and a second array is formed by the second bit lines and the associated word lines;

a plurality of memory cells,

wherein each of the plurality of memory cells is associated with every other bit line alone each word line;

a first plurality of multiplexers,

wherein each of the first plurality of multiplexers is in communication with two adjacent bits lines within one of the first and second arrays;

a second plurality of multiplexers in communication with a voltage source input and with two adjacent bit lines within one of the first and second arrays, wherein the array to which an activated word line belongs acts as a sense array,

wherein the array to which the activated word line does not belong acts as a reference array, and

wherein the DRAM unit comprises;

a dummy word line in the first array; and

a dummy word line in the second array,

wherein the DRAM unit is configured to detect signal levels in a common mode by activating the dummy word line in the reference array and detecting a signal level of the activated word line differentially as compared to a signal level of the activated dummy word line.

12. An apparatus for reducing noise and overall bit line capacitance in a dynamic random access memory (DRAM) device, comprising:

a plurality of pairs of bit line means for conducting electrical signals,

wherein each pair of bit line means includes a first bit line means and a second bit line means,

wherein the first bit line means and the second bit line means within each pair of bit line means are aligned with each other in an end-to-end arrangement,

wherein the first bit line means are arranged substantially parallel and consecutively adjacent to one another,

wherein the second bit line means are arranged substantially parallel and consecutively adjacent to one another;

a plurality of word line means,

wherein each word line means is associated with one of the first bit line means and the second bit line means such that a first array is formed by the first bit line means and the associated word line means and a second array is formed by the second bit line means and the associated word line means;

a plurality of means for storing data,

wherein each of the plurality of means for storing data is associated with every other bit line means along each word line means; and

a first plurality of means for multiplexing,

wherein each of the first plurality of means for multiplexing is in communication with two adjacent bits line means within one of the first and second arrays, wherein said first array acts as a sense array and said second array acts as a reference array for said first array when at least one of said plurality of word line means is active in said first array.

13. The apparatus of claim 12, wherein, for each word line means, each bit line means that is not associated with the plurality of means for storing data acts as a shield between bit line means that are associated with the plurality of means for storing data.

14. The apparatus of claim 12, comprising:

a plurality of means for amplifying,

wherein each of the plurality of means for amplifying is in communication with a means for multiplexing associated with two adjacent first bit line means of the first array and a means for multiplexing associated with two corresponding adjacent second bit line means of the second array.

15. The apparatus of claim 14, comprising:

a second plurality of means for multiplexing in communication with a voltage source input means and with two adjacent bit line means within one of the first and second arrays.

17. The apparatus of claim 12, comprising:

a first interconnect layer means; and

a second interconnect layer means,

wherein each bit line means is associated with both the first and second interconnect layer means.

18. The apparatus of claim 17, wherein the first interconnect layer means comprises a first metal layer and the second interconnect layer means comprises a second metal layer.

19. The apparatus of claim 17, wherein the first interconnect layer means comprises a metal layer and the second interconnect layer means comprises a polysilicon layer.

20. The apparatus of claim 17, wherein the first interconnect layer means comprises a polysilicon layer and the second interconnect layer means comprises a metal layer.

21. The apparatus of claim 12, wherein the DRAM device is manufactured using a logic process.

22. The apparatus of claim 12, wherein the DRAM device is manufactured using a DRAM process.

16. An apparatus for reducing noise and overall bit line capacitance in a dynamic random access memory (DRAM) device, comprising:

a plurality of pairs of bit line means for conducting electrical signals,

wherein each pair of bit line means includes a first bit line means and a second bit line means,

wherein the first bit line means and the second bit line means within each pair of bit line means are aligned with each other in an end-to-end arrangement,

wherein the first bit line means are arranged substantially parallel and consecutively adjacent to one another,

wherein the second bit line means are arranged substantially parallel and consecutively adjacent to one another;

a plurality of word line means,

wherein each word line means is associated with one of the first bit line means and the second bit line means such that a first array is formed by the first bit line means and the associated word line means and a second array is formed by the second bit line means and the associated word line means;

a plurality of means for storing data,

wherein each of the plurality of means for storing data is associated with every other bit line means along each word line means; and

a first plurality of means for multiplexing,

wherein each of the first plurality of means for multiplexing is in communication with two adjacent bits line means within one of the first and second arrays;

a second plurality of means for multiplexing in communication with a voltage source input means and with two adjacent bit line means within one of the first and second arrays;

wherein the array to which the activated word line means does not belong acts as a reference array, and

wherein the apparatus comprises;

a dummy word line means for conducting electrical signals in the first array;

a dummy word line means for conducting electrical signals in the second array; and

means for detecting signal levels in a common mode by activating the dummy word line means in the reference array and for detecting a signal level of the activated word line means differentially as compared to a signal level of the activated dummy word line means.

23. A method of reducing noise and overall bit line capacitance in a dynamic random access memory (DRAM) device, the DRAM device including a plurality of bit line pairs, a plurality of word lines, a plurality of memory cells, and a first plurality of multiplexers wherein each bit line pair includes a first bit line and a second bit line, the method comprising the steps of

(a) aligning the first bit line and the second bit line within each bit line pair in an end-to-end arrangement;

(b) arranging the first bit lines substantially parallel and consecutively adjacent to one another;

(c) arranging the second bit lines substantially parallel and consecutively adjacent to one another;

(d) associating each word line with one of the first bit lines and the second bit lines such that a first array is formed by the first bit lines and the associated word lines and a second array is formed by the second bit lines and the associated word lines;

(e) associating each of the plurality of memory cells with every other bit line along each word line; and

(f) bringing each of the first plurality of multiplexers into communication with two adjacent bits lines within one of the first and second arrays, wherein said first array acts as a sense array and said second array acts as a reference array for said first array when at least one of said plurality of word lines is active in said first array.

24. The method of claim 23, wherein, for each word line, each bit line that is not associated with the plurality of memory cells acts as a shield between bit lines that are associated with the plurality of memory cells.

25. The method of claim 23, wherein the DRAM unit includes a plurality of sense amplifiers, and

wherein the method comprises the step of

(g) bringing each of the plurality of sense amplifiers into communication with a multiplexer associated with two adjacent first bit lines of the first array and a multiplexer associated with two corresponding adjacent second bit lines of the second array.

26. The method of claim 25, wherein the DRAM device includes a second plurality of multiplexers, and

wherein the method comprises the step of

(h) bringing each of the second plurality of multiplexers into 30 communication with a voltage source input and with two adjacent bit lines within one of the first and second arrays.

28. The method of claim 23, wherein the DRAM device includes a first interconnect layer and a second interconnect layer, and

wherein the method comprises the step of:

(g) associating each bit line with both the first and second interconnect layers.

29. The method of claim 28, wherein the first interconnect layer includes a first metal layer and the second interconnect layer includes a second metal layer.

30. The method of claim 28, wherein the first interconnect layer includes a metal layer and the second interconnect layer includes a polysilicon layer.

31. The method of claim 28, wherein the first interconnect layer includes a polysilicon layer and the second interconnect layer includes a metal layer.

32. The method of claim 23, wherein the DRAM device is manufactured using a logic process.

33. The method of claim 23, wherein the DRAM device is manufactured using a DRAM process.

27. A method of reducing noise and overall bit line capacitance in a dynamic random access memory (DRAM) device, the DRAM device including a plurality of bit line pairs, a plurality of word lines, a plurality of memory cells, and a first plurality of multiplexers, wherein each bit line pair includes a first bit line and a second bit line, the method comprising:

(a) aligning the first bit line and the second bit line within each bit line pair in an end-to-end arrangement;

(b) arranging the first bit lines substantially parallel and consecutively adjacent to one another;

(c) arranging the second bit lines substantially parallel and consecutively adjacent to one another;

(d) associating each word line with one of the first bit lines and the second bit lines such that a first array is formed by the first bit lines and the associated word lines and a second array is formed by the second bit lines and the associated word lines;

(e) associating each of the plurality of memory cells with every other bit line along each word line; and

(f) bringing each of the first plurality of multiplexers into communication with two adjacent bits lines within one of the first and second arrays

h) bringing each of the second plurality of multiplexers into communication with a voltage source input and with two adjacent bit lines within one of the first and second arrays;

wherein the array to which the activated word line does not belong acts as a reference array,

wherein the DRAM device further includes a dummy word line in the first array and a dummy word line in the second array; and

(i) detecting signal levels in a common mode by activating the dummy word line in the reference array and detecting a signal level of the activated word line differentially as compared to a signal level of the activated dummy word line.