Method circuit and system for compensating for temperature induced margin loss in non-volatile memory cells

• US 7,184,313 B2
• Filed: 06/17/2005
• Issued: 02/27/2007
• Est. Priority Date: 06/17/2005
• Status: Active Grant

• Current Assignee: Saifun Semiconductors Ltd. (Infineon Technologies AG)
• Original Assignee: Saifun Semiconductors Ltd. (Infineon Technologies AG)
• Inventors: Betser, Yoram, Sofer, Yair, Maayan, Eduardo
• Primary Examiner(s): LE, THONG QUOC
• Application Number:
  US11/155,252
• Publication Number:
  US 20060285408A1
• Time in Patent Office: 620 Days
• Field of Search: 365/185.24
• US Class Current: 365/185.24
• CPC Class Codes: G11C 16/3404 Convergence or correction of memory cell threshold voltages; Repair or recovery of overerased or overprogrammed cells
• CPC Class Codes: G11C 16/3445 Circuits or methods to verify correct erasure of nonvolatile memory cells
• CPC Class Codes: G11C 16/3459 Circuits or methods to verify correct programming of nonvolatile memory cells

Abstract

The present invention consists of a method and system for compensating, over time and over an operating temperature range, for margin loss in a non-volatile memory (“NVM”) cell, which method comprises selection of a reference level based on temperature readings obtained from a temperature sensing element that is thermally coupled, directly or indirectly, to the NVM cell. The reference level may be selected from a group consisting of references levels of various types, or it may be obtained by adjusting the output of a single reference based on the temperature reading(s), or it may be obtained by utilizing pre-stored conversion data, which conversion data associates a given temperature reading with a corresponding temperature range that is, in turn, associated with a corresponding reference level. A pool of likewise reference cells may be provided, and the reference level may be selected from this pool, based on its association to the temperature reading. The pool of reference cells may consist of Program verify reference cells, or Erase verify reference cells.

Claims

1. A method for compensating over time and an operating temperature range for margin loss in non-volatile memory (“

NVM”

) cell of interest, comprising adjusting, or selecting, a reference level based on a signal from a temperature sensing element thermally coupled to the NVM cell, which adjusted, or selected, reference level defining programming and erasing margins in respect of said NVM cell.

2. A method according to claim 1, wherein the reference level is adjusted by manipulating the output of a single reference cell by applying voltages to the gates of the NVM cell and said reference cell, the difference therebetween being dependent on the signal from the temperature sensing element.

3. A method according to claim 1, wherein the reference level is selected by selecting a reference cell from a pool of likewise reference cells based on the signal from the temperature sensing element.

4. A method according to claim 2, wherein the differences between the gates voltages increase as the temperature decreases.

5. A method according to claim 4, wherein the gates voltages difference is obtained based on its association to the temperature signal as stored in a conversion table.

6. A method according to claim 3, wherein the reference cell is selected from a pool of likewise reference cells based on its association to the temperature signal as pre-stored in a conversion table.

7. A method according to claim 2, wherein the adjusted reference cell is a program or an erase verifying reference cell.

8. A method according to claim 3, wherein the selected reference cell is a program or an erase verifying reference cell.

9. A method according to claim 7, wherein the program and erase verifying reference cells are differently adjusted for program and erase verify operations.

10. A method according to claim 8, wherein the program and erase verifying reference cells are differently selected for program and erase verify operations.

11. A method according to claim 9, wherein a reference cell for a program verify operation is selected such that its volt threshold (“

VT”

) is higher as the temperature of the NVM cell increases.

12. A method according to claim 9, wherein a reference cell for an erase verify operation is selected such that its volt threshold (“

VT”

) is lower as the temperature of the NVM cell decreases.

13. A method according to claim 1, wherein the program and/or erase margins are adjusted by adding a constant offset signal either to the NVM cell signal or to the reference cell signal, or both to the NVM cell and reference signals, during program or erase verify operations.

14. A method according to claim 1, wherein the program and erase margins are adjusted by selecting a different reference signal to be used in the program or erase verify operations.

15. A method according to claim 1, wherein the temperature reading is taken according to the following temporal regimes:

the initiation instant of a program or erase operation;

the initiation instant of a program verify or erase verify operation;

at least once during a program, erase, or a verify operation; and

the readings are taken intermittently or continuously.

16. A method according to claim 1, wherein the non-volatile memory cell and reference cell are NROM-type non-volatile memory cells.

17. A system for compensating over time and an operating temperature range for margin loss in non-volatile memory (“

NVM”

) cell of interest in a NVM array of cells, comprising;

a) a temperature sensing element(s) substantially thermally coupled to said cell or to said NVM array of cells, or to preferred portions thereof;

b) a reference module operative to provide a reference level based on a signal from said temperature sensing element(s), against which said cell of interest is to be compared, which reference level defines program and erase margins;

c) a sensing and readout module for performing the comparisons;

d) an ‘

X-Y’

driving and selection module operative to select the cell of interest from the NVM array of cells;

e) a control logic operative to accept temperature readings from said temperature sensing element(s) for controlling the operation of said ‘

X-Y’

driving and selection module and said reference module for performing program erase or reading operations on of said NVM cell;

wherein said control logic is operative to accept a signal from said sensing and readout module to indicate the completion of said operations; and

f) A power supply block for energizing the other modules.

18. A system according to claim 17, further comprising means for adjusting the reference level, which means adjusting the output of a single reference cell by applying voltages to the gates of the NVM cell of interest and said reference cell, the difference therebetween being dependent on the signal from the temperature sensing element.

19. A system according to claim 17, further comprising a pool of likewise reference cells from which the reference level is selected based on the signal from the temperature sensing element.

20. A system according to claim 18, in which the differences between the gates voltages increase as the temperature decreases.

21. A system according to claim 18, in which the gates voltages difference is obtained based on its association to a corresponding temperature range that is stored in a conversion table.

22. A system according to claim 20, in which the gates voltages difference is obtained based on its association to a corresponding temperature range that is stored in a conversion table.

23. A system according to claim 19, further comprising a conversion table, wherein the reference cell is selected from the pool of likewise reference cells based on its association to a corresponding temperature range that is stored in said conversion table.

24. A system according to claim 18 in which the adjusted reference cell is a program or an erase verifying reference cell.

25. A system according to claim 19, in which the selected reference cell is a program or an erase verifying reference cell.

26. A system according to claim 24, in which the program and erase verifying reference cells are differently adjusted for program and erase verify operations.

27. A system according to claim 25, in which the program and erase verifying reference cells are differently selected for program and erase verify operations.

28. A system according to claim 27, in which a reference cell for a program verify operation is selected such that its volt threshold (“

VT”

) is higher as the temperature of the NVM cell increases.

29. A system according to claim 27, in which a reference cell for an erase verify operation is selected such that its volt threshold (“

VT”

) is lower as the temperature of the NVM cell decreases.

30. A system according to claim 17, in which the program and/or erase margins are adjusted by adding a constant offset signal either to the NVM cell signal or to the reference cell signal, or both to the NVM cell and reference signals, during program or erase verify operations.

31. A system according to claim 17, in which the program and erase margins are adjusted by selecting a different reference signal to be used in the program or erase verify operations.

32. A system according to claim 17, in which the temperature reading is taken according to one of the following temporal regimes:

at the initiation of a program or erase operation;

the temperature reading is taken at the initiation of a program verify or erase verify operation;

the temperature reading is taken at least once during a program, erase, or a verify operation; and

temperature readings are taken intermittently or continuously.

33. A system according to claim 17, wherein the non-volatile memory array of cells and reference cells are NROM-type non-volatile memory cells.

34. A circuit for compensating over time and an operating temperature range for margin loss in non-volatile memory (“

NVM”

) cell of interest, comprising;

a) a temperature sensing element substantially thermally coupled to said NVM cell;

b) a controller operative to select a reference level based on a signal from said temperature sensor, and to utilize it to perform program, erase or reading operation on said NVM cell, which reference level defining program and erase margins in respect of said NVM cell;

c) adjusting means for adjusting the reference level by adjusting the output of a single reference cell by applying voltages to the gates of the NVM cell of interest and said reference cell, the difference therebetween being dependent on the signal from the temperature sensing element;

d) a pool of likewise reference cells from which the reference level is selected based on the signal from the temperature sensing element’

;

e) conversion table, for selecting the reference cell from the pool of likewise reference cells based on its association to a corresponding temperature range that is pre-stored in said conversion table;

wherein,

the differences between the gates voltages increase as the temperature decreases, and

wherein

the gates voltages difference is obtained based on its association to a corresponding temperature range that is pre-stored in a conversion table, and wherein the adjusted, or selected, reference cell is a program or an erase verifying reference cell, and wherein the program and erase verifying reference cells are differently adjusted or selected for program and erase verify operations, and wherein a reference cell for a program verify operation is selected such that its volt threshold (“

VT”

) is higher as the temperature of the NVM cell increases, and wherein a reference cell for an erase verify operation is selected such that its volt threshold (“

VT”

) is lower as the temperature of the NVM cell decreases, and wherein the program and/or erase margins are adjusted by adding a constant offset signal either to the NVM cell signal or to the reference cell signal, or both to the NVM cell and reference signals, during program or erase verify operations, and wherein the program and erase margins are adjusted by selecting a different reference signal to be used in the program or erase verify operations, and wherein the temperature reading is taken at the initiation of a program or erase operation or is taken at the initiation of a program verify or erase verify operation or it is taken at least once during a program, erase, or a verify operation or the temperature readings are taken intermittently or continuously.