Semiconductor device, semiconductor device testing method, and programming method

• US 7,184,338 B2
• Filed: 08/30/2005
• Issued: 02/27/2007
• Est. Priority Date: 08/30/2004
• Status: Expired due to Fees

• Current Assignee: Valley Device Management
• Original Assignee: Spansion LLC (Infineon Technologies AG)
• Inventors: Aoki, Minoru, Yamada, Shigekazu, Nakagawa, Harunobu
• Primary Examiner(s): Phung; Anh
• Assistant Examiner(s): Bernstein; Allison
• Application Number:
  US11/215,253
• Publication Number:
  US 20060077736A1
• Time in Patent Office: 546 Days
• Field of Search: 365/201, 365/189.03
• US Class Current: 365/201
• CPC Class Codes: G11C 16/04 using variable threshold transistors, e.g. FAMOS
• CPC Class Codes: G11C 16/12 Programming voltage switching circuits
• CPC Class Codes: G11C 2029/5004 Voltage
• CPC Class Codes: G11C 29/02 Detection or location of defective auxiliary circuits, e.g. defective refresh counters
• CPC Class Codes: G11C 29/021 in voltage or current generators
• CPC Class Codes: G11C 29/028 with adaption or trimming of parameters
• CPC Class Codes: G11C 29/50 Marginal testing, e.g. race, voltage or current testing
• CPC Class Codes: G11C 29/50004 of threshold voltage

Abstract

A semiconductor device includes: a latch circuit that latches a given signal in a test mode; and a generating circuit that generates a signal that defines a program voltage used for programming of a memory cell in accordance with the signal latched in the latch circuit. The generating circuit includes: a circuit that generates the signal that defines an initial voltage of the program voltage; a circuit that generates the signal that defines a pulse width of the program voltage; and a circuit that generates the signal that defines a step width of the program voltage when the program voltage is a voltage that increases stepwise.

Claims

1. A semiconductor device comprising:

a latch circuit that latches a given signal in a test mode; and

a generating circuit that generates a signal that defines a pulse width of a program voltage used for programming of a memory cell in accordance with the signal latched in the latch circuit.

2. The semiconductor device as claimed in claim 1, wherein the generating circuit generates the signal that defines an initial voltage of the program voltage.

3. The semiconductor device as claimed in claim 1, wherein the generating circuit generates the signal that defines a step width of the program voltage when the program voltage is a voltage that increases stepwise.

4. The semiconductor device as claimed in claim 1, wherein:

the generating circuit generates the signal that defines a step width of the program voltage when the program voltage is a voltage that increases stepwise; and

the semiconductor device further comprises a voltage control circuit that controls a switch that selects a capacitor in accordance with the signal that defines the step width of the program voltage.

5. The semiconductor device as claimed in claim 1, wherein the latch circuit is connected to a given address terminal, and the given signal is an address signal applied via the address terminal.

6. The semiconductor device as claimed in claim 1, further comprising a sense amplifier circuit that outputs verification data from cell data read out from the memory cell during a given period for verification in the test mode.

7. The semiconductor device as claimed in claim 1, further comprising a reference circuit that selects a specific reference cell from a plurality of reference cells used for verification in accordance with the given signal latched in the latch circuit.

8. The semiconductor device as claimed in claim 1, wherein the latch circuit latches given signals in accordance with signals provided to the latch circuit.

9. The semiconductor device as claimed in claim 1, further comprising a non-volatile memory that stores the given signal latched in the latch circuit.

10. The semiconductor device as claimed in claim 1, further comprising:

a non-volatile memory that stores the given signal latched in the latch circuit; and

a control circuit that generates the signal that defines the program voltage in accordance with the given signal stored in the non-volatile memory.

11. The semiconductor device as claimed in claim 1, wherein the memory cell has multiple threshold values.

12. The semiconductor device as claimed in claim 11, wherein the program voltage increases stepwise for each of multiple threshold values of the memory cell.

13. A method of testing a semiconductor device comprising the steps of:

latching a given signal in a test mode; and

generating a signal that defines a step width of a program voltage used for programming of a memory cell in accordance with the given signal latched.

14. The method as claimed in claim 13, wherein the step of generating comprises the step of generating the signal that defines an initial voltage of the program voltage.

15. The method as claimed in claim 13, wherein the step of generating comprises the step of generating the signal that defines a pulse width of the program voltage in accordance with the given signal latched.

16. A semiconductor device comprising:

a write circuit that writes data having multiple levels into memory cells with multiple threshold values; and

a generating circuit that generates, for each of the multiple levels, a signal that defines a program voltage that increases stepwise.

17. The semiconductor device as claimed in claim 16, wherein the generating circuit includes a circuit that generates, for each of the multiple levels, the signal that defines a step width of the program voltage.

18. The semiconductor device as claimed in claim 16, wherein the generating circuit includes a circuit that generates, for each of the multiple levels, the signal that defines a pulse width of the program voltage.

19. The semiconductor device as claimed in claim 16, wherein the generating circuit includes a circuit that generates, when programming is involved in a last one of the multiple levels, the signal that defines the program voltage having a pulse width greater than pulse widths of program voltages used for the multiple levels other than the last one.

20. The semiconductor device as claimed in claim 16, further comprising a detection circuit that detects a situation in which the program voltage reaches a given voltage, wherein the generating circuit includes a circuit that generates, when programming is involved in a last one of the multiple levels, the signal that defines the program voltage having a pulse width greater than pulse widths of program voltages used for the multiple levels other than the last one after the detection circuit detects the situation.

21. The semiconductor device as claimed in claim 16, wherein the generating circuit comprises:

a latch circuit that latches the program voltage at a given timing when programming is involved in a first level among the multiple levels; and

a circuit that generates another signal that defines a second level following the first level on the basis of an initial program voltage corresponding to the program voltage latched in the latch circuit.

22. The semiconductor device as claimed in claim 21, wherein the given timing is defined as the timing at which verification for programming involved in the first level passes.

23. The semiconductor device as claimed in claim 16, wherein the generating circuit is a control circuit that controls the write circuit.

24. A semiconductor device comprising:

a write circuit that writes data having multiple levels into a memory cell with multiple threshold values; and

a control circuit that controls the write circuit and performs programming involved in a last one of the multiple levels with a program voltage having a pulse width greater than pulse widths used in programming involved in the multiple levels other than the last one.

25. A semiconductor device comprising:

a write circuit that writes data having multiple levels into memory cells with multiple threshold values; and

a control circuit that controls the write circuit and performs programming so that a program voltage increases stepwise without verification until the program voltage reaches a given voltage when the programming is involved in a last one of the multiple levels.

26. The semiconductor device as claimed in claim 25, further comprising a detection circuit that detects a situation in which the program voltage reaches a given voltage,

wherein the control circuit performs programming so that the program voltage increases stepwise until the program voltage reaches the given voltage and performs programming involved in the last one of the multiple levels so that a program voltage is provided having a pulse width greater than pulse widths used in programming involved in the multiple levels other than the last one.

27. A semiconductor device comprising:

a write circuit that writes data having multiple levels into memory cells with multiple threshold values; and

a control circuit that controls the write circuit and performs programming involved in a first level out of the multiple levels so that a program voltage increases stepwise while storing the program voltage ata given timing, and performs programming involved in a second level out of the multiple levels so that an initial voltage corresponding to the program voltage stored increases stepwise.

28. The semiconductor device as claimed in claim 27, further comprising a latch circuit that latches the program voltage at the given timing.

29. The semiconductor device as claimed in claim 27, wherein the given timing is defined as the timing at which verification for programming involved in the first level passes.

30. The semiconductor device as claimed in claim 27, wherein the semiconductor device is a semiconductor memory device.

31. A programming method comprising the steps of:

performing programming involved in a first one of multiple levels of data that is written into a memory cell with multiple threshold values while increasing a program voltage stepwise;

storing the program voltage at a given timing in the step of performing; and

performing programming involved in a second one of the multiple levels following the first one while increasing, stepwise, an initial program voltage corresponding to the program voltage stored in the step of storing.

32. A programming method comprising the steps of:

performing programming involved in multiple levels except a last level while increasing a program voltage stepwise; and

performing programming involved in the last level by using the program voltage having a pulse width greater than pulse widths of the program voltages used in programming involved in the multiple levels except the last level.

33. A programming method comprising the steps of:

performing programming involved in multiple levels except a last level while increasing a program voltage stepwise; and

performing programming involved in the last level while increasing the program voltage stepwise without verification for said programming until the program voltage reaches a given voltage.