High speed precision pseudo random noise shift control for fast multiple channel global positioning system signal re-tracking
First Claim
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1. An apparatus comprising:
- a control circuit to generate a channel enable signal based on control information from a processor at a first clock signal having a first clock frequency, the channel enable signal selecting a channel for a satellite in a global positioning system (GPS), the channel operating at a coarse/acquisition (C/A) clock signal having a second clock frequency, the control information including at least one of channel select information, an initial count, an increment value, and PN command;
an increment register to store the increment value for the selected channel at the first clock signal; and
an accumulator coupled to the increment register and the control circuit to generate a PN clock signal using the increment value;
wherein the control circuit comprises;
a decoder to decode the channel select information, the decoded channel select information providing the channel enable signal;
a channel enable register coupled to the decoder to store the channel enable signal at the first clock signal;
a counter coupled to the channel enable register to update a count from the initial count at the first clock signal, the counter generating a terminal signal when the count reaches a terminal count; and
a logic circuit coupled to the counter and the channel enable register to generate a load signal from the PN command to load the initial count to the counter and a reset signal from the terminal signal to reset the channel enable register.
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Abstract
One embodiment of the present invention includes a control circuit, an increment register, and an accumulator. The control circuit generates a channel enable signal based on control information from a processor at a first clock signal having a first clock frequency. The channel enable signal selects a channel for a satellite in a global positioning system (GPS). The channel operates at a coarse/acquisition (C/A) clock signal having a second clock frequency. The increment register stores an increment value for the selected channel at the first clock signal. The accumulator generates a pseudo-random noise (PN) clock signal to a PN generator using the increment value.
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Citations
24 Claims
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1. An apparatus comprising:
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a control circuit to generate a channel enable signal based on control information from a processor at a first clock signal having a first clock frequency, the channel enable signal selecting a channel for a satellite in a global positioning system (GPS), the channel operating at a coarse/acquisition (C/A) clock signal having a second clock frequency, the control information including at least one of channel select information, an initial count, an increment value, and PN command; an increment register to store the increment value for the selected channel at the first clock signal; and an accumulator coupled to the increment register and the control circuit to generate a PN clock signal using the increment value; wherein the control circuit comprises; a decoder to decode the channel select information, the decoded channel select information providing the channel enable signal; a channel enable register coupled to the decoder to store the channel enable signal at the first clock signal; a counter coupled to the channel enable register to update a count from the initial count at the first clock signal, the counter generating a terminal signal when the count reaches a terminal count; and a logic circuit coupled to the counter and the channel enable register to generate a load signal from the PN command to load the initial count to the counter and a reset signal from the terminal signal to reset the channel enable register. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A method comprising:
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generating a channel enable signal based on control information from a processor at a first clock signal having a first clock frequency, the channel enable signal selecting a channel for a satellite in a global positioning system (GPS), the channel operating at a coarse/acquisition (C/A) clock signal having a second clock frequency, the control information including at least one of channel select information, an initial count, an increment value, and PN command; storing the increment value for the selected channel at the first clock signal; and generating a pseudo-random noise (PN) clock signal to a PN generator using the increment value; wherein generating the channel enable signal comprises; decoding the channel select information, the decoded channel select information providing the channel enable signal; storing the channel enable signal at the first clock signal; updating a count from the initial count at the first clock signal to generate a terminal signal when the count reaches a terminal count; and generating a load signal from the PN command to load the initial count to the counter and a reset signal from the terminal signal to reset the channel enable register. - View Dependent Claims (10, 11, 12, 13, 14, 15, 16)
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17. A receiver comprising:
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a processor to generate control information including at least one of channel select information, an initial count, an increment value, and PN command; a pseudo-random noise (PN) code generator to generate a PN sequence at a PN clock signal to a correlator of a global positioning system (GPS) base-band system; and a code numerically controlled oscillator (NCO) coupled to the PN code generator and the processor to generate the PN clock signal based on the control information, the code NCO comprising; a control circuit to generate a channel enable signal based on the control information at a first clock signal having a first clock frequency, the channel enable signal selecting a channel for a satellite in a global positioning system (GPS), the channel operating at a coarse/acquisition (C/A) clock signal having a second clock frequency, an increment register to store the increment value for the selected channel at the first clock signal, and an accumulator coupled to the increment register and the control circuit to generate the PN clock signal using the increment value; wherein the control circuit comprises; a decoder to decode the channel select information, the decoded channel select information providing the channel enable signal; a channel enable register coupled to the decoder to store the channel enable signal at the first clock signal; a counter coupled to the channel enable register to update a count from the initial count at the first clock signal, the counter generating a terminal signal when the count reaches a terminal count; and a logic circuit coupled to the counter and the channel enable register to generate a load signal from the PN command to load the initial count to the counter and a reset signal from the terminal signal to reset the channel enable register. - View Dependent Claims (18, 19, 20, 21, 22, 23, 24)
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Specification