Column address path circuit and method for memory devices having a burst access mode

• US 7,185,173 B2
• Filed: 01/24/2005
• Issued: 02/27/2007
• Est. Priority Date: 03/09/2001
• Status: Expired due to Term

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Ho, Duc V.
• Primary Examiner(s): NGUYEN, THAN VINH
• Application Number:
  US11/043,018
• Publication Number:
  US 20050201183A1
• Time in Patent Office: 764 Days
• Field of Search: None
• US Class Current: 711/220
• CPC Class Codes: G11C 11/4087 Address decoders, e.g. bit - or word line decoders; Multiple line decoders
• CPC Class Codes: G11C 7/1018 Serial bit line access mode, e.g. using bit line address shift registers, bit line address counters, bit line burst counters

Abstract

Column addresses are generated by a burst controller that includes respective latches for the three low-order bits of a column address. The two higher order bits of the latched address bits and their compliments are applied to respective first multiplexers along with respective bits from a burst counter. The first multiplexers apply the latched address bits and their compliments to respective second multiplexers during a first bit of a burst access, and bits from a burst counter during the remaining bits of the burst. The second multiplexers are operable responsive to a control signal to couple either the latched address bits or their compliments to respective outputs for use as an internal address. The control signal is generated by an adder logic circuit that receives the two low-order bits of the column address. The adder logic circuit processes the column address bits at the same time the address bits are being coupled through the second multiplexer to the first multiplexer as a function of the correct relationship between the internal address bits and the external address bits.

Claims

1. A method of generating a bit in each of a plurality of internal address, the method comprising:

receiving a first external address;

providing an incrementing address;

generating a complement of at least one bit of the first external address, and

initially selecting the at least one bit and its complement;

subsequently selecting a bit of the incrementing address;

examining at least one bit of the first external address; and

based on the examination, coupling to an output terminal one of the selected bits to provide a bit for each of a plurality of internal addresses.

2. The method of claim 1 wherein the first external address comprises an external column address.

3. The method of claim 1 wherein the act of examining at least one bit of the external address comprises examining at least one bit of the external address to determine its relationship to at least one other bit of the external address.

4. The method of claim 1, further comprising determining an operating mode, and wherein the acts of coupling to an output terminal one of the selected bits based on the examination comprises coupling to an output terminal one of the selected bits based on a combination of the examination of at least one bit of the external address and the determined operating mode.

5. The method of claim 4 wherein the determined operating mode comprises a serial or interleaved operating mode.

6. The method of claim 4 wherein the determined operating mode comprises the length of an address burst.

7. A method of generating a bit in each of a plurality of internal address, the method comprising:

processing a first bit of an external address;

initially coupling a bit of the external address and its complement through a first signal path;

subsequently coupling a bit of an incrementing address through the first signal path; and

selecting a bit coupled to the first signal path based on the processing of the first bit of the external address.

8. The method of claim 7 wherein the external address comprises an external column address.

9. The method of claim 7 wherein the act of processing a first bit of the external address comprises determine the value of the bit in relationship to the value of another bit of the external address.

10. The method of claim 7 wherein the act of processing a first bit of the external address comprises determining an operating mode.

11. The method of claim 10 wherein the determined operating mode comprises either a serial operating mode or an interleaved operating mode.

12. The method of claim 10 wherein the determined operating mode comprises the length of an address burst.

13. A method of generating a sequence of internal address bits based on at least one external address bit, comprising:

initially selecting either the at least one external address bit and its complement;

determining the correct relationship between at least one external address bit and the corresponding bit of an internal address;

based on the determined correct relationship, selecting either the at least one external address bit or its complement, and using the selected at least one external address bit or its complement as a first internal address bit in the sequence of internal address bits; and

using a corresponding bit of an incrementing address as subsequent internal address bits in the sequence of internal address bits.

14. The method of claim 13 wherein the external address bit comprises an external column address bit.

15. The method of claim 13, further comprising determining an operating mode, and wherein the act of selecting one of the initially selected bits comprises selecting one of the initially selected bits based on a combination of the determined correct relationship and the determined operating mode.

16. The method of claim 15 wherein the determined operating mode comprises either a serial operating mode or an interleaved operating mode.

17. The method of claim 15 wherein the determined operating mode comprises the length of an address burst.