Atomic update of CPO state

• US 7,185,183 B1
• Filed: 08/02/2001
• Issued: 02/27/2007
• Est. Priority Date: 08/02/2001
• Status: Expired due to Term

• Current Assignee: MIPS Tech, LLC
• Original Assignee: MIPS Technologies Incorporated (Wave Computing, Inc.)
• Inventors: Uhler, G. Michael
• Primary Examiner(s): Coleman, Eric
• Application Number:
  US09/921,400
• Time in Patent Office: 2,035 Days
• Field of Search: 712/229, 712/224, 712/244
• US Class Current: 712/224
• CPC Class Codes: G06F 9/30018 Bit or string instructions
• CPC Class Codes: G06F 9/30038 using a mask
• CPC Class Codes: G06F 9/3004 to perform operations on memory
• CPC Class Codes: G06F 9/30087 Synchronisation or serialisation instructions
• CPC Class Codes: G06F 9/30145 Instruction analysis, e.g. decoding, instruction word fields

Abstract

A group of bit set and bit clear instructions are provided for a microprocessor to allow atomic modification of privileged architecture control registers. The bit set and bit clear instructions include an opcode that designates to the microprocessor that the instructions are to execute in privileged (kernel) state only, and that the instructions are to communicate with privileged control registers. Two operands are provided for the instructions, the first designating which of the privileged control registers is to be modified, the second designating a general purpose register that contains a bit mask. The bit set instructions set bits in the designated control register according to bits set in the bit mask. The bit clear instructions clear bits in the designated control register according to bits set in the bit mask. By atomically modifying privileged control registers, a requirement for strict nesting of interrupt routines is eliminated.

Claims

1. A microprocessor having a control register that is atomically modifiable by a privileged (kernel) instruction, the control register having bit fields, the microprocessor comprising:

a core, for receiving the privileged instruction and for atomically modifying the control register upon execution of the privileged instruction, wherein the control register is not accessible when the microprocessor is executing unprivileged instructions;

the privileged instruction comprising;

an opcode, for identifying the instruction as a privileged instruction;

a first operand, for specifying the control register as a register to be modified; and

a second operand, for specifying a location of a second register within the microprocessor, said second register containing a bit mask, said bit mask determining which of the bit fields within the control register are to be modified;

wherein said bit mask is used to atomically set or clear the bit fields in the control register;

whereby the bit fields in the control register are modified atomically by the privileged instruction.

2. The microprocessor as recited in claim 1, wherein the control register is modified by the privileged instruction in a single cycle.

3. The microprocessor as recited in claim 1 wherein the control register is directly modified by the privileged instruction without requiring the contents of the control register to first be moved to a general purpose (i.e., non-privileged) register.

4. The microprocessor as recited in claim 1 wherein the privileged instruction is executed when the microprocessor receives an interrupt signal.

5. The microprocessor as recited in claim 1 wherein the privileged instruction comprises:

a first instruction, for setting bit fields in the control register according to the contents of said bit mask;

or

a second instruction, for clearing bit fields in the control register according to the contents of said bit mask.

6. The microprocessor as recited in claim 5 wherein said first instruction sets bit fields in the control register pertaining to corresponding bits that are set in said bit mask.

7. The microprocessor as recited in claim 5 wherein said second instruction clears bit fields in the control register pertaining to corresponding bits that are set in said bit mask.

8. The microprocessor as recited in claim 1 wherein said second register comprises a general purpose register.

9. The microprocessor as recited in claim 1 wherein the privileged instruction further comprises a field for specifying whether the bit fields in the control register are to be set or cleared according to said bit mask.

10. The microprocessor as recited in claim 1 wherein the control register comprises:

an interrupt mask bit field, said interrupt mask bit field having a plurality of bits, each of said plurality of bits for identifying interrupts received by the microprocessor.

11. The microprocessor as recited in claim 10 wherein by atomically clearing one of said plurality of bits using the privileged instruction, its corresponding interrupt is temporarily disabled.

12. A method for atomically modifying bits within a privileged control register of a microprocessor, the method comprising:

providing a privileged instruction which instructs the microprocessor to atomically modify specified ones of the bits, wherein the control register is not accessible when the microprocessor is executing unprivileged instructions;

providing a register, for specifying which of the particular ones of the bits are to be modified; and

upon receipt of an interrupt by the microprocessor, atomically clearing the particular ones of the bits as specified by the register.

13. The method as recited in claim 12 wherein the bits specify which of a plurality of interrupts have been received by the microprocessor.

14. The method as recited in claim 12 wherein the bits specify which of a plurality of interrupts are enabled.

15. The method as recited in claim 12 wherein the privileged control register comprises a status register having a plurality of bit fields, including the bits.

16. The method as recited in claim 12 wherein the privileged instruction comprises:

an opcode for designating the privileged instruction as privileged;

a first operand for designating the privileged control register as the register to be modified; and

a second operand for designating the location of the register.

20. The method as recited in claim 12, wherein the control register is modified by the privileged instruction in a single cycle.

17. A tangible computer readable medium comprising program instructions executable by a microprocessor, wherein the program instructions include program code for receiving and executing a privileged instruction, wherein when executed the privileged instruction is operable to:

modify a control register of the microprocessor, wherein the control register is not accessible when the microprocessor is executing unprivileged instructions;

wherein the privileged instruction comprises;

an opcode, for identifying the instruction as a privileged instruction;

a first operand, for specifying the control register as a register to be modified; and

a second operand, for specifying a location of a second register within the microprocessor, said second register containing a bit mask, said bit mask determining which of the bit fields within the control register are to be modified;

wherein said bit mask is used to set or clear the bit fields in the control register;

whereby the bit fields in the control register are modified atomically by the privileged instruction.

18. The tangible computer readable medium as recited in claim 17 wherein the privileged instruction is executed when the microprocessor receives an interrupt signal.

19. The tangible computer readable medium as recited in claim 17 wherein the privileged instruction clears bit fields in the control register pertaining to corresponding bits that are set in said bit mask.

21. The tangible computer readable medium as recited in claim 17, wherein when executed, the privileged instruction is configured to modify the control register in a single cycle.