Multiple-thread processor with in-pipeline, thread selectable storage

• US 7,185,185 B2
• Filed: 03/31/2003
• Issued: 02/27/2007
• Est. Priority Date: 05/11/1999
• Status: Expired due to Term

• Current Assignee: Sun Microsystems Incorporated (Oracle Corporation)
• Original Assignee: Sun Microsystems Incorporated (Oracle Corporation)
• Inventors: Chamdani, Joseph I., Tremblay, Marc, Lauterbach, Gary, Joy, William
• Primary Examiner(s): Coleman; Eric
• Application Number:
  US10/403,406
• Publication Number:
  US 20030191927A1
• Time in Patent Office: 1,429 Days
• Field of Search: 712/228, 712/23
• US Class Current: 712/228
• CPC Class Codes: G06F 12/0842 for multiprocessing or multitasking
• CPC Class Codes: G06F 9/30127 Register windows
• CPC Class Codes: G06F 9/30141 Implementation provisions of register files, e.g. ports
• CPC Class Codes: G06F 9/3804 for branches, e.g. hedging, branch folding
• CPC Class Codes: G06F 9/3851 from multiple instruction streams, e.g. multistreaming
• CPC Class Codes: G06F 9/3885 using a plurality of independent parallel functional units
• CPC Class Codes: G06F 9/4843 by program, e.g. task dispatcher, supervisor, operating system

Abstract

A processor reduces wasted cycle time resulting from stalling and idling, and increases the proportion of execution time, by supporting and implementing both vertical multithreading and horizontal multithreading. Vertical multithreading permits overlapping or “hiding” of cache miss wait times. In vertical multithreading, multiple hardware threads share the same processor pipeline. A hardware thread is typically a process, a lightweight process, a native thread, or the like in an operating system that supports multithreading. Horizontal multithreading increases parallelism within the processor circuit structure, for example within a single integrated circuit die that makes up a single-chip processor. To further increase system parallelism in some processor embodiments, multiple processor cores are formed in a single die. Advances in on-chip multiprocessor horizontal threading are gained as processor core sizes are reduced through technological advancements.

Claims

1. A vertically multi-threaded processor comprising:

a register file structure replicated to simultaneously represent register state for at least two threads; and

at least one pipeline sharable amongst the two threads and coupled to the register file structure, the sharable pipeline including replicated thread selectable storage elements defined therein, whereby the processor freezes in the pipeline, for later resumption, active state of the pipeline and resumes a previously frozen state of the pipeline to facilitate rapid context switch between the two threads.

2. The vertically multi-threaded processor of claim 1,

wherein the rapid context switch is performed without draining the sharable pipeline of state represented therein.

3. The vertically multi-threaded processor of claim 1,

wherein the rapid context switch is performed without storing the frozen thread'"'"'s register state.

4. The vertically multi-threaded processor of claim 1, embodied in a computer system with plural cooperating instances of thereof, the computer system thereby supporting both vertical and horizontal multithreading.

5. The vertically multi-threaded processor of claim 4,

wherein the plural instances are defined on a single semiconductor integrated circuit die.

6. The vertically multi-threaded processor of claim 1,

wherein the rapid context switch is performed in a time period no greater than a nanosecond.

7. The vertically multi-threaded processor of claim 1,

wherein the rapid context switch is completed within a nanosecond range period.

8. The vertically multi-threaded processor of claim 1,

wherein the replicated thread selectable storage includes multiple-bit thread selectable flip-flops that are distributed throughout the pipeline, and which store the active and frozen states of the pipeline in respective bits thereof.

9. The vertically multi-threaded processor of claim 8,

wherein the multiple-bit thread selectable flip-flops are 2-bit, thread selectable flip-flops.

10. The vertically multi-threaded processor of claim 8,

wherein the pipeline is further sharable amongst a total of N threads, N>

2; and

wherein the multi-bit thread selectable flip-flops are N-bit, thread selectable flip-flops.

11. The vertically multi-threaded processor of claim 1,

wherein the replicated thread selectable storage includes register stages defined internal to the pipeline, wherein individual bit positions of the register stages are represented using N-bit, thread selectable flip-flops, N≧

2, the individual bits thereof representing a respective portion of pipeline register state for a thread active in the pipeline and for up to N−

1 additional threads suspended therein.

12. The vertically multi-threaded processor of claim 11,

wherein N=2.

13. The vertically multi-threaded processor of claim 1, further comprising:

separate load store units for each of the two threads.

14. The vertically multi-threaded processor of claim 1, further comprising:

at least one additional pipeline operable in parallel with the at least one shareable pipeline, thereby supporting horizontal multi-threading in addition to the vertical multi-threading.

15. The vertically multi-threaded processor of claim 1,

wherein the rapid context switch is responsive to stall of a thread currently active in the shareable pipeline.

16. The vertically multi-threaded processor of claim 1, wherein the rapid context switch is responsive to one or more of:

a stall signal;

a periodic signal; and

a scheduler signal.

17. A method of operating a multi-Threaded processor, the method comprising:

executing plural threads;

simultaneously representing, in a register file structure, register state for a least two of the threads; and

simultaneously representing respective pipeline states for the two threads, the respective pipeline states being represented in a pipeline shared amongst the two threads using replicated thread selectable storage elements defined in the shared pipeline itself; and

performing a rapid context switch between the two threads at least in part by freezing in the shared pipeline, for later resumption, active state of the shared pipeline and by resuming a previously frozen state of the shared pipeline.

18. The method of claim 17, further comprising:

performing the rapid context switch without draining the shared pipeline of state represented therein.

19. The method of claim 17, further comprising:

performing the rapid context switch without storing the frozen thread'"'"'s register state.

20. The method of claim 17, further comprising:

executing at least one additional thread in an additional pipeline operable in parallel with the shared pipeline, thereby supporting horizontal multi-threading in addition to vertical multi-threading.

21. The method of claim 17, further comprising:

performing the rapid context switch in a time period no greater than a nanosecond.

22. The method of claim 17, further comprising:

completing the rapid context switch within a nanosecond range period.

23. The method of claim 17,

wherein the replicated tread selectable storage includes multiple-bit thread selectable flip-flops that are distributed throughout the shared pipeline, and which store the active and frozen states of the shared pipeline in respective bits thereof.

24. The method of claim 23,

wherein the multiple-bit thread selectable flip-flops are 2-bit, thread selectable flip-flops.

25. The method of claim 23,

wherein the pipeline is further shamble amongst a total of N threads, N≦

2; and

wherein the multi-bit tread selectable flip-flops are N-bit, thread selectable flip-flops.

26. The method of claim 17,

wherein the replicated tread selectable storage includes register stages defined internal to the shared pipeline, wherein individual bit positions of the register stages are represented using N-bit, tread selectable flip-flops, N≧

2, individual bits thereof representing a respective portion of pipeline register state for a thread active in the shred pipeline and for up to N−

1 additional threads suspended therein.

27. The method of claim 26,

wherein N=2.

28. The method of claim 17, further comprising:

performing the rapid context switch responsive to stall of a thread currently active in the shared pipeline.

29. The method of claim 17, further comprising:

performing the rapid context switch responsive to one or more of;

a stall signal;

a periodic signal; and

a scheduler signal.

30. A multi-threaded processor that simultaneously represents in thread selectable storage that is distributed throughout a pipeline thereof both active and frozen states of the pipeline, the thread selectable storage facilitating rapid context switch between threads corresponding to the active and frozen states.

31. The multi-threaded processor of claim 30,

wherein the rapid context switch is performed without draining the pipeline of state represented therein.

32. A processor comprising:

a first multiple-thread processor core including a multiple-thread pipeline, the multiple-thread pipeline including a plurality of multiple-bit thread-selectable flip-flops, the multiple-bit thread-selectable flip-flops selecting pipeline state corresponding to an active thread from amongst pipeline states stored in the multiple-thread pipeline for a plurality of execution threads.

33. The processor of claim 32, further comprising:

a register file that includes a plurality of storage structures that are replicated to represent register state of respective of the execution threads.

34. The processor of claim 32, further comprising:

a second multiple-Thread processor core substantially identical to the first.

35. The processor of claim 32,

wherein at least some of the multiple-bit, thread-selectable flip-flops are organized to define multiple-bit, thread selectable pipeline registers.

36. The processor of claim 32, further comprising:

a metal layer interconnecting the multiple-bit, thread-selectable flip-flops.

37. The processor of claim 32, further comprising:

backend logic coupled to the multiple-thread pipeline and including interface units for interfacing to an external cache and a memory, the backend logic being shared amongst the plurality of execution threads and including single-bit flip-flops.

38. A method of making a multi-threaded processor product, the method comprising:

converting a single-thread processor core to a multiple-threaded processor core at least in part by substituting for pipeline registers that include single-bit flip-flops, respective multiple-bit pipeline registers embodied as collections of multiple-bit, thread-selectable flip-flops;

maintaining substantially the same semiconductor footprint for the multiple-bit, thread-selectable flip-flops as for the single-bit flip-flops; and

fabricating the multi-threaded processor product with the substituted multiple-bit, thread-selectable flip-flops.

39. The method of claim 38, further comprising:

maintaining in the fabricated the multi-threaded processor product, area, aspect ratio, and terminal connections of the single-thread processor.

40. An apparatus comprising:

first means for simultaneously representing register state for a least two threads executing in a processor; and

second means for simultaneously representing in a first pipeline, respective pipeline states for the two threads;

wherein the pipeline state corresponding to one of the two threads is active and wherein the pipeline state corresponding to the other of the two threads is frozen therein.

41. An apparatus as in claim 40, further comprising:

means for performing rapid context switch between the two threads at least in part by freezing in the pipeline, for later resumption, active state of the first pipeline and by resuming a previously frozen state of the first pipeline.

42. An apparatus as in claim 40, further comprising:

an additional pipeline executable in parallel with the first.