Data processing

• US 7,185,208 B2
• Filed: 09/27/2002
• Issued: 02/27/2007
• Est. Priority Date: 09/28/2001
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Lexar Media Incorporated (Micron Technology, Inc.)
• Inventors: Gorobets, Sergey Anatolievich
• Primary Examiner(s): Zand; Kambiz
• Application Number:
  US10/260,136
• Publication Number:
  US 20030126451A1
• Time in Patent Office: 1,614 Days
• Field of Search: 713/189, 713/193
• US Class Current: 713/193
• CPC Class Codes: G06F 12/1408 by using cryptography for digital transmission H04L9/00
• CPC Class Codes: G06F 21/6209 to a single file or object, e.g. in a secure envelope, encrypted and accessed using a key, or with access control rules appended to the object itself
• CPC Class Codes: G06F 21/79 in semiconductor storage media, e.g. directly-addressable memories
• CPC Class Codes: G06F 2221/2107 File encryption

Abstract

In one embodiment of the present invention, there is disclosed a reversible method of processing data comprising the data being encrypted before being written to a non-volatile memory wherein the data cannot be accessed without decryption in the case of a direct physical access to the non-volatile memory.

Claims

1. A method of processing sector data before being written or stored in non-volatile memory comprising:

Receiving sector data for writing to the non-volatile memory, the sector data including user data and associate header data;

Storing the received sector data in byte portions within a buffer memory; and

Encrypting the sector data before the sector data is written to non-volatile memory wherein a scrambling function is performed to modify the address of the byte portions to mix the byte portions when the same is stored within the non-volatile memory so that the byte portions are each located at an address within the non-volatile memory which is different from the original address of the byte portions within the buffer memory.

2. A method of processing data, as recited in claim 1, further including retrieving the scrambled sector data to form retrieved scrambled sector data and decrypting the retrieved scrambled sector data by using a descrambling function on the byte portions of the retrieved data.

3. A method of processing data, as recited in claim 1, wherein performing the scrambling function ‘

on the fly’

.

4. A memory system for receiving sector data from a host system and for writing thereof comprising:

non-volatile memory arranged to present the logical characteristics of a disc storage device to a host system; and

a controller having buffer memory and for managing sector data transfers to and from the non-volatile memory, the controller being adapted reversibly to encrypt the sector data before the sector data is written to non-volatile memory wherein a scrambling function is performed to modify the address of the byte portions to mix the byte portions when the same is stored within the non-volatile memory so that the byte portions are each located at an address within the non-volatile memory which is different from the original address of the byte portions within the buffer memory.

5. A memory system, as recited in claim 4, wherein the sector data includes user data and associate header data.

6. A memory system, as recited in claim 5, wherein the scrambling function acts to modify the byte address of each byte portion within the buffer memory.

7. A memory system, as recited in claim 6, wherein, the scrambling function scrambles together the user data and header data.

8. A memory system, as recited in claim 7, including a first converter for performing the scrambling function.

9. A memory system, as recited in claim 6, wherein the scrambling function is performed ‘

on the fly’

.

10. A memory system, as recited in claim 6, wherein the scrambling function is parameterized by the address of the sector.

11. A memory system, as recited in claim 6, wherein the user data is used as a parameter.

12. A memory system, as recited in claim 6, further including a second converter for encoding every portion of the scrambled sector data using an encoding function D1.

13. A memory system, as recited in claim 12, further including an ECC block generator coupled between the buffer memory and the non-volatile memory for scrambling and encoding the sector data to generate an ECC field.

14. A memory system, as recited in claim 12, further including a third converter for further encoding the scrambled and encoded data using an encoding function D2.

15. A memory system, as recited in claim 14, wherein the encoding functions D1 and D2 are performed with parameters in the same manner.

16. A memory system for receiving sector data from a host system and for writing thereof comprising:

non-volatile memory arranged to present the logical characteristics of a disc storage device to a host system; and

a controller having buffer memory and for managing sector data transfers to and from the non-volatile memory, the controller being adapted reversibly to encrypt the sector data before the sector data is written to non-volatile memory, the sector data including user data and associate header data wherein a scrambling function is performed to modify the address of the byte portions to mix the byte portions when the same is stored within the non-volatile memory so that the byte portions are each located at an address within the non-volatile memory which is different from the original address of the byte portions within the buffer memory, wherein the scrambling function acts to modify the byte address of each byte portion within the buffer memory;

a first converter for encoding every portion of the scrambled sector data using an encoding function D1;

a third converter for further encoding the scrambled and encoded data using an encoding function D2;

a third converter for receiving the scrambled and encoded data D1 and D2 and the ECC field for performing an encoding function thereon using an encoding function D3 on each portion of the sector data thus providing encrypted data which is sent to the non-volatile memory.

wherein the encoding functions D1 and D2 are performed with parameters in the same manner.

17. A memory system, as recited in claim 16, wherein the first and second converters are used to perform decoding functions when data is being read from the non-volatile memory.