Semiconductor integrated circuit and electronic system

• US 7,185,244 B2
• Filed: 04/14/2004
• Issued: 02/27/2007
• Est. Priority Date: 06/26/2003
• Status: Expired due to Fees

• Current Assignee: Renesas Technology Corporation (Renesas Electronics Corporation)
• Original Assignee: Renesas Technology Corporation (Renesas Electronics Corporation)
• Inventors: Kitamura, Teruo, Kojima, Hirotsugu
• Primary Examiner(s): Kerveros; James C.
• Application Number:
  US10/823,581
• Publication Number:
  US 20040264227A1
• Time in Patent Office: 1,049 Days
• Field of Search: 714/724, 714/718, 714/726, 327/157, 327/158, 331/17
• US Class Current: 714/718
• CPC Class Codes: G11C 16/0433 comprising cells containing a single floating gate transistor and one or more separate select transistors
• CPC Class Codes: G11C 16/0441 comprising cells containing multiple floating gate devices, e.g. separate read-and-write FAMOS transistors with connected floating gates
• CPC Class Codes: G11C 2216/10 Floating gate memory cells with a single polysilicon layer
• CPC Class Codes: G11C 29/02 Detection or location of defective auxiliary circuits, e.g. defective refresh counters
• CPC Class Codes: G11C 29/028 with adaption or trimming of parameters
• CPC Class Codes: G11C 29/12015 comprising clock generation or timing circuitry
• CPC Class Codes: G11C 29/50012 of timing
• CPC Class Codes: G11C 7/1006 Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor

Abstract

The invention provides a semiconductor integrated circuit for communication control and a wireless communication system using the same realizing reduction in the size of a chip and the size of a module by enabling trimming data to be written into a nonvolatile memory without increasing the number of external terminals. A rewritable nonvolatile memory is provided in a semiconductor integrated circuit, characteristics of circuits including an electronic part are measured and trimming data for correcting variations in the characteristics is stored in the nonvolatile memory. A pin and an interface circuit such as a test pin and a JTAG interface circuit which are originally provided for the semiconductor integrated circuit also serve as an input pin and an interface circuit for sending and storing the trimming data to the nonvolatile memory.

Claims

1. A semiconductor integrated circuit comprising:

a rewritable nonvolatile memory for storing first trimming data formed on the semiconductor integrated circuit;

an interface circuit for test coupled to said nonvolatile memory,

a digital to analog converter coupled to the nonvolatile memory; and

a register coupled to the digital to analog converter for storing second trimming data;

wherein the digital to analog converter receives the stored first trimming data from said nonvolatile memory and receives the second trimming data from the register and outputs adjustment data, and

wherein said nonvolatile memory stores said trimming data for correcting a change in circuit characteristics which occurs due to variations in electronic parts or devices, via said interface circuit for test.

2. The semiconductor integrated circuit according to claim 1, further comprising:

a terminal for outputting the adjustment data.

3. The semiconductor integrated circuit according to claim 1, further comprising:

a microprocessor for executing control in accordance with commands of a program; and

a program memory for storing said program commands executed by the microprocessor,

wherein said microprocessor reads the adjustment data stored in said nonvolatile.

4. The semiconductor integrated circuit according to claim 1, wherein said electronic part is a quartz oscillator, and said adjustment data is data for adjusting an oscillation frequency of an oscillating circuit including said quartz oscillator.

5. The semiconductor integrated circuit according to claim 1, wherein the first trimming data is upper bit trimming data and the second trimming data is lower bit trimming data.

6. The semiconductor integrated circuit according to claim 5, wherein the register is coupled to the microprocessor and the microprocessor determines the lower bit trimming data to synchronize a slave clock to a master clock.

7. An electronic system comprising:

an electronic part;

a first semiconductor integrated circuit including;

a first nonvolatile memory formed on the said first semiconductor integrated circuit,

a microprocessor coupled to the first nonvolatile memory and configured to execute a sequence of programmed instructions,

an interface circuit for test coupled to the first nonvolatile memory,

a second nonvolatile memory coupled to the microprocessor for storing said instructions executed by the microprocessor,

wherein said first nonvolatile memory stores first trimming data for correcting a change in circuit characteristics which occurs due to variations in said electronic part;

a digital to analog converter coupled to the first nonvolatile memory; and

a register coupled to the digital to analog converter for storing second trimming data;

wherein the digital to analog converter receives the stored first trimming data from said first nonvolatile memory and receives the second trimming data from the lower bit register and outputs adjustment data; and

a substrate over which the electronic part and the first semiconductor integrated circuit are mounted,

wherein said first nonvolatile memory is rewritable for storing updated first trimming data.

8. The electronic system according to claim 7, wherein said first nonvolatile memory stores said first trimming data received via a terminal, wherein the terminal is a test terminal provided over said substrate.

9. The electronic system according to claim 7, wherein said first semiconductor integrated circuit has an interface circuit for test, and wherein said first nonvolatile memory stores said adjustment data received via said interface circuit for test.

10. The electronic system according to claim 7, wherein said second nonvolatile memory is a mask ROM.

11. The electronic system according to claim 7, wherein said electronic part is a quartz oscillator, and said adjustment data is data for adjusting an oscillation frequency of an oscillating circuit including said quartz oscillator.

12. The electronic system according to claim 11, further comprising a second semiconductor integrated circuit in which a device is formed that provides an oscillating circuit when coupled to said quartz oscillator,

wherein a clock signal generated by said second semiconductor integrated circuit is supplied as a reference clock signal to said first semiconductor integrated circuit.

13. The electronic system according to claim 12, wherein said first semiconductor integrated circuit is a semiconductor integrated circuit for performing a baseband signal process for communication, and said second semiconductor integrated circuit is a semiconductor integrated circuit having a radio frequency transmission/reception function.

14. The semiconductor integrated circuit according to claim 8, wherein the first trimming data is upper bit trimming data and the second trimming data is lower bit trimming data.

15. The electronic system according to claim 14, wherein the register is coupled to the microprocessor and the microprocessor determines the lower bit trimming data to synchronize a slave clock to a master clock.

16. A semiconductor integrated circuit comprising:

a rewritable nonvolatile memory formed on the semiconductor integrated circuit;

an interface circuit for test coupled to the nonvolatile memory,

a digital to analog converter coupled to the nonvolatile memory; and

a register coupled to the digital to analog converter for storing second trimming data;

wherein the digital to analog converter receives the stored first trimming data from said nonvolatile memory and receives the second trimming data from the register and outputs adjustment data, and

wherein said nonvolatile memory stores said first trimming data for correcting a change in circuit characteristics caused by variations in electronic parts or devices, and data peculiar to the semiconductor integrated circuit, via said interface circuit for test.

17. The semiconductor integrated circuit according to claim 16, wherein said electronic part is a quartz oscillator, and said adjustment data is data for adjusting oscillation frequency of an oscillating circuit including said quartz oscillator.

18. The semiconductor integrated circuit according to claim 16, wherein the second trimming data is lower bit trimming data.

19. The semiconductor integrated circuit according to claim 18, wherein the register is coupled to the microprocessor and the microprocessor determines the lower bit trimming data to synchronize a slave clock to a master clock.