Compacting circuit responses
First Claim
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1. A method comprising:
- providing a compactor characterized by a binary matrix having a row for each of a plurality of circuit elements and a column for each compactor output;
making all of the matrix rows non-zero and different from each of the other rows; and
making all of the matrix rows have an odd number of ones.
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Abstract
Circuit responses to a stimulus may be compacted, decreasing the number of pin outs, without increasing the circuit element length, using a compactor. In accordance with one embodiment of the present invention, errors may be detected in scan chains used for integrated circuit testing. The number of outputs applied to output pins or other connectors may be substantially decreased, resulting in cost savings.
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Citations
25 Claims
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1. A method comprising:
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providing a compactor characterized by a binary matrix having a row for each of a plurality of circuit elements and a column for each compactor output; making all of the matrix rows non-zero and different from each of the other rows; and making all of the matrix rows have an odd number of ones. - View Dependent Claims (2, 3, 4)
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5. A device comprising:
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n input terminals, where n is an integer value of at least 2; m output terminals where m is less than n; and said device having a binary matrix having a row for each of a plurality of circuit elements and column for each output, all of the matrix rows being non-zero and each of said rows being different from each of the other rows, wherein all of said matrix rows have an odd number of ones. - View Dependent Claims (6, 7, 8)
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9. A method comprising:
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providing a compactor characterized by a binary matrix having a row for each of a plurality of scan chains and a column for each compactor output; making all of the matrix rows non-zero and different from each of the other rows; and forming a compactor matrix using exclusive OR gates. - View Dependent Claims (10, 11)
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12. A device to compact scan chain responses comprising:
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n input terminals; m output terminals, where m is less than n; said device having a binary matrix having a row for each of a plurality of circuit elements and a column for each output, all of the matrix rows being non-zero and all of said rows being different from each of the other rows; and an array of exclusive OR gates. - View Dependent Claims (13, 14, 15, 16, 17)
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18. A method comprising:
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coupling a plurality of inputs to a smaller number of outputs through exclusive OR gates; coupling said inputs to said outputs so that at least one exclusive OR gate is coupled between each input and at least one output; coupling said inputs to said outputs so that each input is coupled to said outputs differently; and designing a compactor using the principles that if a single scan chain produces an error at any scan out, the compactor outputs produce an error at that scan cycle if, and only if, no row of the compactor matrix contains all zeros, if two scan chains produce errors at any scan out cycle, the compactor outputs produce an error at that cycle if, and only if, no two rows of a compactor matrix are identical, where three or an odd number of scan chains produce errors at any scan out cycle, the compact outputs produce an error at that scan out cycle if, and only if, the bitwise exclusive-OR of any two rows of a compactor matrix is not equal to any other row of the compactor matrix, if a scan chain produces an error and another scan chain produces a logic value unknown during simulation in any scan out cycle, the compactor outputs produce an error at that scan out cycle if, and only if, no row of the compactor matrix contains all zeros, and if any two rows have one at the same column there must be two columns in which the same rows have (0,1) and (1,0) and differentiating the situation where a single scan chain produces an error at the scan out cycle and the compactor outputs produce an error at that scan out cycle if, and only if, the bitwise exclusive-OR of any two rows of the compactor matrix is not equal to any other row of the compactor matrix, and if the bitwise exclusive-OR of two rows of a compactor matrix is equal to a compactor error vector at the scan out cycle, then it is possible that the scan chains corresponding to these two rows produce errors at that scan out cycle. - View Dependent Claims (19, 20, 21, 22, 23, 24, 25)
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Specification