Non-volatile DRAM and a method of making thereof

• US 7,186,612 B2
• Filed: 04/06/2004
• Issued: 03/06/2007
• Est. Priority Date: 01/28/2004
• Status: Expired due to Fees

• Current Assignee: 021C Incorporated
• Original Assignee: O2ic, Inc.
• Inventors: Choi, Kyu Hyun
• Primary Examiner(s): Huynh; Andy
• Application Number:
  US10/819,596
• Publication Number:
  US 20050161718A1
• Time in Patent Office: 1,064 Days
• Field of Search: 438/238, 438/239, 438/386
• US Class Current: 438/238
• CPC Class Codes: H01L 27/105 including field-effect components
• CPC Class Codes: H10B 12/00 Dynamic random access memory [DRAM] devices
• CPC Class Codes: H10B 12/09 with simultaneous manufacture of the peripheral circuit region and memory cells
• CPC Class Codes: H10B 41/40 characterised by the peripheral circuit region
• CPC Class Codes: H10B 41/49 comprising different types of peripheral transistor
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
• CPC Class Codes: H10B 99/00 Subject matter not provided for in other groups of this subclass

Abstract

A method of forming a non-volatile DRAM includes, in part, forming a first polysilicon layer above a first dielectric layer to form a control gate of the non-volatile device of the non-volatile DRAM; forming sidewall spacers adjacent the first polysilicon layer; forming a second oxide layer; forming a second polysilicon layer above the second oxide layer, forming lightly doped areas in the body region; forming a second spacer above the body region, forming source and drain regions of the non-volatile device and the MOS transistor of the non-volatile DRAM; forming a third polysilicon layer over portions of the lightly doped areas to form polysilicon landing pads; forming a third dielectric layer above the polysilicon landing pads; and forming a fourth polysilicon layer over the third dielectric layer.

Claims

1. A method of making an integrated circuit in a semiconductor substrate, the method comprising:

forming at least two isolation regions in the semiconductor substrate;

forming a well between the two isolation regions, the well defining a body region;

forming a first oxide layer above a first portion of the body region;

forming a first dielectric layer above the first oxide layer;

forming a first polysilicon layer above said first dielectric layer, said first polysilicon layer forming a control gate of a non-volatile device;

forming a second dielectric layer above the first polysilicon layer;

forming a first spacer above the body region and adjacent said first polysilicon layer;

forming a second oxide layer above a second portion of the body region not covered by said first spacer;

forming a second polysilicon layer above the second oxide layer, the first spacer and a portion of the second dielectric layer;

said second polysilicon layer forming a guiding gate of the non-volatile device and a gate of an MOS transistor;

forming lightly doped areas in the body region;

forming a second spacer above the body region to define source and drain regions of the non-volatile device and source and drain regions of the MOS transistor;

delivering second implants to the defined source and drain regions;

forming a third polysilicon layer over portions of the lightly doped areas in the body region to form polysilicon landing pads;

forming a third dielectric layer over the formed polysilicon landing pads; and

forming a fourth polysilicon layer over the third dielectric layer.

2. The method of claim 1 further comprising:

forming a salicide layer over the portions of the lightly doped areas in the body region that form polysilicon landing pads.

3. The method of claim 2 further comprising:

forming a metal layer over the salicide layer to form a bitline and a terminal adapted to receive a supply voltage.

4. The method of claim 3 wherein a doping concentration of the first implants delivered to one of the source and drain regions of the non-volatile device is greater than a doping concentration of the first implants delivered to the other one of the source and drain regions of the non-volatile device.

5. The method of claim 4 wherein said first dielectric layer further includes an oxide layer and a nitride layer.

6. The method of claim 5 wherein said second dielectric layer further includes an oxide layer and a nitride layer.

7. The method of claim 6 wherein said well is a p-well.

8. The method of claim 7 further comprising:

forming an n-well below the p-well.

9. The method of claim 8 wherein said n-well is formed using at least one implant step.

10. The method of claim 9 wherein at least two implant steps are used to form the n-well using a same mask.

11. The method of claim 10 wherein said second oxide layer has a thickness greater than the thickness of the first oxide layer.