Power transistor arrangement and method for fabricating it

• US 7,186,618 B2
• Filed: 10/29/2004
• Issued: 03/06/2007
• Est. Priority Date: 10/30/2003
• Status: Active Grant

• Current Assignee: Infineon Technologies AG
• Original Assignee: Infineon Technologies AG
• Inventors: Rieger, Walter, Kotek, Manfred, Hirler, Franz, Haberlen, Oliver, Polzl, Martin
• Primary Examiner(s): CHAUDHARI, CHANDRA P
• Application Number:
  US10/977,118
• Publication Number:
  US 20050145936A1
• Time in Patent Office: 858 Days
• Field of Search: 438/140, 438/270, 438/589, 257/E21.419
• US Class Current: 438/270
• CPC Class Codes: H01L 29/402 Field plates
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/41741 for vertical or pseudo-vertical devices
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

When fabricating trench power transistor arrangements (1) with active cell array trenches (5) and passive connecting trenches (6), the cell array trenches (5) are provided in greater width than the connecting trenches (6). An auxiliary layer (24) is deposited conformally onto a lower field electrode structure (11) in the cell array trenches (5) and the connecting trenches (6) and is etched back as far as the top edge in the connecting trenches (6), which removes it from the cell array trenches (5). The auxiliary layer (24) allows the gate oxide (20) to be patterned without a complex mask process. An edge trench (7), with an electrode, on the potential of the field electrode structure (11) shields the cell array (3) from a drain potential.

Claims

1. A method for fabricating a power transistor arrangement, comprising:

providing a cell array in a semiconductor substrate including a substrate surface;

providing a plurality of cell array trenches and at least one connecting trench connected to the plurality of cell array trenches within the cell array, wherein the width of each of the plurality of cell array trenches is greater than the width of the at least one connecting trench, and wherein the plurality of cell array trenches and at least one connecting trench extend below the substrate surface;

providing an insulating layer on the substrate surface and in the plurality of cell array trenches and at least one connecting trench;

applying a first conductive layer to the insulating layer;

at least partially removing the first conductive layer, wherein the first conductive layer forms a field electrode structure;

applying a conductive auxiliary layer to the insulating layer and the first conductive layer, wherein the at least one connecting trench is filled with the conductive auxiliary layer and the plurality of cell array trenches are lined with the conductive auxiliary layer;

removing the conductive auxiliary layer from the plurality of cell array trenches and at least partially removing the conductive auxiliary layer in the at least one connecting trench; and

forming a gate electrode structure in the plurality of cell array trenches;

wherein the field electrode structure contacts a region of the at least one connecting trench, and wherein the at least one connecting trench connects the plurality of cell array trenches.

2. The method as claimed in claim 1 wherein the gate electrode structure is formed by the steps of:

removing portions of the insulating layer which are covered neither by the first conductive layer nor by the auxiliary layer;

applying a gate insulating layer;

applying a second conductive layer; and

at least partially removing the second conductive layer to substantially the level of the substrate surface in the plurality of cell array trenches.

3. The method as claimed in claim 1 wherein the step of providing a plurality of cell array trenches and at least one connecting trench further includes providing an edge trench, the edge trench surrounding the cell array in the semiconductor substrate, and wherein the width of the edge trench is substantially the same as the width of the at least one connecting trench.

4. The method as claimed in claim 1 wherein the step of forming the gate electrode structure is followed by the steps of:

applying an intermediate oxide layer;

providing a source contact trench in the intermediate oxide layer and in the semiconductor substrate between two of the plurality of cell array trenches, the source contact trench operable to conductively connect a source region and the at least one connecting trench to a source metallization;

providing a plurality of gate contact holes operable to conductively connect the gate electrode structure to a gate metallization, and

applying the gate metallization and the source metallization.

5. The method as claimed in claim 4 wherein the at least one connecting trench is provided running at right angles with respect to the plurality of cell array trenches and to the source contact trench.

6. The method as claimed in claim 1 wherein the material provided for the conductive auxiliary layer is a material which can be removed selectively with respect to the material of the first conductive layer.

7. The method as claimed in claim 1 wherein the material provided for the second conductive layer is doped polysilicon.

8. A method of making a power transistor arrangement having a transistor edge termination, the method comprising:

providing a cell array in a semiconductor substrate including a substrate surface;

providing in the semiconductor substrate a plurality of cell array trenches and at least one edge trench which surrounds the cell array and forms the transistor edge termination, the plurality of cell array trenches being greater in width than the at least one edge trench;

applying an insulating layer to the substrate surface and in the plurality of cell array trenches and the at least one edge trench;

applying a conductive auxiliary layer to the insulating layer, wherein the at least one edge trench is filled with the conductive auxiliary layer and the plurality of cell array trenches are lined with the conductive auxiliary layer;

removing the conductive auxiliary layer from the plurality of cell array trenches and at least partially removing the conductive auxiliary layer in the at least one edge trench to substantially the level of the substrate surface, wherein removal of the conductive auxiliary layer provides exposed portions of the insulating layer;

removing the exposed portions of the insulating layer;

applying a gate insulating layer;

applying a second conductive layer to form a gate electrode structure; and

at least partially removing the second conductive layer to substantially the level as the substrate surface, thereby forming the gate electrode structure from the second conductive layer.

9. The method as claimed in claim 8 wherein the gate insulating layer is applied by means of oxidation of semiconductor material.

10. The method as claimed in claim 8 wherein the insulating layer is applied by growing or depositing a field oxide.

11. The method as claimed in claim 8 wherein the second conductive layer is applied by conformally depositing doped polysilicon.

12. The method as claimed in claim 8 wherein the conductive auxiliary layer is applied using a conformal deposition process and is at least partially removed using an isotropic etching process.

13. The method as claimed in claim 8 further comprising the step of providing source regions in the semiconductor substrate by implanting a dopant.

14. The method as claimed in claim 8 further comprising the step of performing silicidation of the gate electrode structure following formation of the gate electrode structure.

15. The method as claimed in claim 8 wherein the plurality of cell array trenches comprise inner cell array trenches and an outer cell array trench, wherein the inner cell array trenches are formed parallel to one another, and wherein the outer cell array trench include first trench portions which are formed parallel to the inner cell array trenches and second trench portions which are formed at right angles to the inner cell array trenches, and wherein the inner cell array trenches are connected to the second trench portions of the outer cell array trench.

16. The method as claimed in claim 15 wherein a minimum distance between the outer cell array trench and the inner cell array trenches corresponds to a distance between two adjacent inner cell array trenches.

17. The method as claimed in claim 15 wherein the outer cell array trench includes finger-like extensions arranged and disposed to make contact with the gate electrode structure.

18. The method as claimed in claim 15 wherein the at least one edge trench and the outer cell array trench are connected to one another by a connecting trench.