Silicon on insulator (SOI) negative differential resistance (NDR) based memory device with reduced body effects

• US 7,187,028 B2
• Filed: 01/13/2005
• Issued: 03/06/2007
• Est. Priority Date: 06/28/2002
• Status: Expired due to Term

• Current Assignee: Synopsys Incorporated
• Original Assignee: Synopsys Incorporated
• Inventors: King, Tsu-Jae
• Primary Examiner(s): MENZ, DOUGLAS M
• Application Number:
  US11/035,786
• Publication Number:
  US 20050121664A1
• Time in Patent Office: 782 Days
• Field of Search: 257/25, 257/314, 257/326
• US Class Current: 257/314
• CPC Class Codes: G11C 11/40 using transistors
• CPC Class Codes: G11C 2211/5614 Multilevel memory cell comprising negative resistance, quantum tunneling or resonance tunneling elements

Abstract

A silicon-on-insulator (SOI) memory device (such as an SRAM) using negative differential resistance (NDR) elements is disclosed. Body effect performances for NDR FETs (and other FETs) that may be used in such device are enhanced by floating a body of some/all the NDR FETs.

Claims

1. In a silicon on insulator (SOI) based memory device having three active elements, including a transfer field effect transistor (FET), a first negative differential resistance (NDR) element and a second NDR element that are operably interconnected to store a data value, the improvement comprising:

at least one of the first NDR element and the second NDR element being implemented as a SOI-based NDR-capable FET,

wherein a contact is provided to a body region of the SOI-based NDR capable FET so as to provide a bias signal and operate the SOI based memory device in a non-floating body effect mode,

wherein said SOI-based NDR capable FET includes a charge trap region adapted for rapidly trapping and de-trapping charge to effectuate an NDR characteristic.

2. The SOI based memory device of claim 1, wherein said charge trap region is formed between a channel region and a gate region of said SOI-based NDR capable FET.

3. The SOI based memory device of claim 1, wherein said SOI-based NDR capable FET includes a body with a net P-type dopant concentration.

4. In a silicon on insulator (SOI) based memory device having three active elements, including a transfer field effect transistor (FET), a first negative differential resistance (NDR) element and a second NDR element that are operably interconnected to store a data value, the improvement comprising:

at least one of the first NDR element and the second NDR element being implemented as a SOI-based NDR-capable FET,

wherein a contact is provided to a body region of the SOI-based NDR capable FET so as to provide a bias signal and operate the SOI based memory device in a non-floating body effect mode,

wherein said second NDR element is a tunneling diode and/or an NDR capable FET.