System and method for providing a fast turn on bias circuit for current mode logic transmitters

• US 7,187,212 B1
• Filed: 10/26/2004
• Issued: 03/06/2007
• Est. Priority Date: 10/26/2004
• Status: Active Grant

• Current Assignee: National Semiconductor Corporation (Texas Instruments, Inc.)
• Original Assignee: National Semiconductor Corporation (Texas Instruments, Inc.)
• Inventors: Lewicki, Laurence D., Segervall, Alan E.
• Primary Examiner(s): Tan; Vibol
• Assistant Examiner(s): WHITE, DYLAN C
• Application Number:
  US10/973,220
• Time in Patent Office: 861 Days
• Field of Search: 326/115, 326/126, 326/127
• US Class Current: 326/127
• CPC Class Codes: H03K 19/0016 by using a control or a clock signal, e.g. in order to apply power supply

Abstract

A system and method is disclosed for providing a fast turn on bias circuit that permits a fast transition from an idle “power down” state to an active “power up” state in current mode logic (CML) transmitter output circuits. The invention comprises a capacitor coupled to a bias transistor and a charge switch circuit for controlling the operation of the capacitor. The capacitor has a value of capacitance that is equal in magnitude and opposite in sign to the Miller coupling capacitance in the bias transistor. The capacitor compensates for the Miller coupling capacitance within the bias transistor in less than ten nanoseconds. This permits a CML transmitter to more quickly restart the transmission of data after an active state has been initiated.

Claims

1. A fast turn on bias circuit capable of being coupled to a gate of a bias transistor, said fast turn on bias circuit capable of providing a value of capacitance to said gate of said bias transistor to compensate for a Miller coupling capacitance in said bias transistor, said fast turn on bias circuit comprising:

a capacitor having an output capable of being coupled to said gate of said bias transistor; and

a charge switch circuit coupled to an input of said capacitor.

2. The fast turn on bias circuit as set forth in claim 1 wherein said capacitor comprises a transistor configured as a capacitor.

3. The fast turn on bias circuit as set forth in claim 1 wherein said capacitor has a value of capacitance that is equal in magnitude and opposite in sign to said Miller coupling capacitance in said bias transistor.

4. The fast turn on bias circuit as set forth in claim 3 wherein said charge switch circuit in response to control signals one of:

enables an operation of said capacitor and disables an operation of said capacitor.

5. The fast turn on bias circuit as set forth in claim 4 wherein said charge switch circuit comprises:

a first transistor having an output coupled to an input of said capacitor and having a gate coupled to a first input control signal; and

a second transistor having an output coupled to said input of said capacitor and having a gate coupled to a second input control signal;

wherein said second input control signal is an inverted version of said first input control signal.

6. The fast turn on bias circuit as set forth in claim 5 wherein said charge switch circuit further comprises:

a third transistor and a fourth transistor coupled together in the form of an inverter circuit, said inverter circuit having as an input said first input control signal and having as an output said second input control signal;

wherein said output of said inverter circuit is coupled to said gate of said second transistor.

7. The fast turn on bias circuit as set forth in claim 4 wherein said charge switch circuit receives a control signal to enable an operation of said capacitor when a drain voltage of said bias transistor is increasing.

8. The fast turn on bias circuit as set forth in claim 4 wherein said charge switch circuit receives a control signal to disable an operation of said capacitor when a drain voltage of said bias transistor is decreasing.

9. The fast turn on bias circuit as set forth in claim 3 wherein said capacitor provides a value of capacitance to said bias transistor to compensate for said Miller coupling capacitance in said bias transistor in less than ten nanoseconds.

10. A common mode logic (CML) transmitter output circuit comprising a bias transistor and a fast turn on bias circuit capable of being coupled to a gate of said bias transistor, said fast turn on bias circuit capable of providing a value of capacitance to said gate of said bias transistor to compensate for a Miller coupling capacitance in said bias transistor, said fast turn on bias circuit comprising:

a capacitor having an output capable of being coupled to said gate of said bias transistor; and

a charge switch circuit coupled to an input of said capacitor.

11. The common mode logic (CML) transmitter output circuit as set forth in claim 10 wherein said capacitor of said fast turn on bias circuit comprises a transistor configured as a capacitor.

12. The common mode logic (CML) transmitter output circuit as set forth in claim 10 wherein said capacitor of said fast turn on bias circuit has a value of capacitance that is equal in magnitude and opposite in sign to said Miller coupling capacitance in said bias transistor.

13. The common mode logic (CML) transmitter output circuit as set forth in claim 12 wherein said charge switch circuit of said fast turn on bias circuit in response to control signals one of:

enables an operation of said capacitor and disables an operation of said capacitor.

14. The common mode logic (CML) transmitter output circuit as set forth in claim 13 wherein said charge switch circuit of said fast turn on bias circuit comprises:

a first transistor having an output coupled to an input of said capacitor and having a gate coupled to a first input control signal; and

a second transistor having an output coupled to said input of said capacitor and having a gate coupled to a second input control signal;

wherein said second input control signal is an inverted version of said first input control signal.

15. The common mode logic (CML) transmitter output circuit as set forth in claim 14 wherein said charge switch circuit of said fast turn on bias circuit further comprises:

a third transistor and a fourth transistor coupled together in the form of an inverter circuit, said inverter circuit having as an input said first input control signal and having as an output said second input control signal;

wherein said output of said inverter circuit is coupled to said gate of said second transistor.

16. The common mode logic (CML) transmitter output circuit as set forth in claim 13 wherein said charge switch circuit of said fast turn on bias circuit receives a control signal to enable an operation of said capacitor when a drain voltage of said bias transistor is increasing.

17. The common mode logic (CML) transmitter output circuit as set forth in claim 13 wherein said charge switch circuit of said fast turn on bias circuit receives a control signal to disable an operation of said capacitor when a drain voltage of said bias transistor is decreasing.

18. The common mode logic (CML) transmitter output circuit as set forth in claim 12 wherein said capacitor of said fast turn on bias circuit provides a value of capacitance to said bias transistor to compensate for said Miller coupling capacitance in said bias transistor in less than ten nanoseconds.

19. A fast turn on bias circuit capable of being coupled to a gate of a bias transistor, said fast turn on bias circuit capable of providing a plurality of values of capacitance to said gate of said bias transistor to compensate for a Miller coupling capacitance in said bias transistor, said fast turn on bias circuit comprising:

a plurality of capacitors of different values, each of said plurality of capacitors having an output capable of being coupled to said gate of said bias transistor; and

a charge switch circuit coupled to an input of each of said plurality of capacitors.

20. The fast turn on bias circuit as set forth in claim 19 wherein each of said plurality of capacitors comprises a transitory configured as a capacitor.

21. The fast turn on bias circuit as set forth in claim 19 wherein a plurality of said capacitors have a combined value of capacitance that is equal in magnitude and opposite in sign to said Miller coupling capacitance in said bias transistor.

22. The fast turn on bias circuit as set forth in claim 21 wherein said charge switch circuit in response to control signals enables an operation of a first portion of said plurality of capacitors and disables an operation of a second portion of said plurality of capacitors.

23. The fast turn on bias circuit as set forth in claim 19 wherein said bias transistor is a bias transistor in a common mode logic (CML) transmitter output circuit.

24. The fast turn on bias circuit as set forth in claim 23 wherein said fast turn on bias circuit provides a value of capacitance to said bias transistor of said common mode logic (CML) transmitter output circuit to compensate for said Miller coupling capacitance in said bias transistor in less than ten nanoseconds.