Method and system for providing current balanced writing for memory cells and magnetic devices

• US 7,187,577 B1
• Filed: 11/23/2005
• Issued: 03/06/2007
• Est. Priority Date: 11/23/2005
• Status: Active Grant

• Current Assignee: Samsung Semiconductor Incorporated (Samsung Electronics Co. Ltd.)
• Original Assignee: Grandis, Inc. (Samsung Electronics Co. Ltd.)
• Inventors: Diao, Zhitao, Ding, Yunfei, Wang, Lien-Chang
• Primary Examiner(s): Nguyen; Tuan T.
• Application Number:
  US11/286,083
• Time in Patent Office: 468 Days
• Field of Search: 365/158, 365/148
• US Class Current: 365/158
• CPC Class Codes: G11C 11/16 using elements in which the storage effect is based on magnetic spin effect

Abstract

A method and system for providing a magnetic memory is included. The method and system include providing at least one magnetic storage cell and at least one dummy resistor coupled with the at least one magnetic storage cell at least for a write operation of the at least one magnetic storage cell. Each of the at least one magnetic storage cell includes a magnetic element and a selection device coupled with the magnetic element. The magnetic element being programmed by a first write current driven through the magnetic element in a first direction and a second write current driven through the magnetic element in a second direction. The selection device is configured to be coupled between the magnetic element and the at least one dummy resistor.

Claims

1. A magnetic memory comprising:

at least one magnetic storage cell, each of the at least one magnetic storage cell including a magnetic element and a selection device coupled with the magnetic element, the magnetic element being programmed by a first write current driven through the magnetic element in a first direction and a second write current driven through the magnetic element in a second direction; and

at least one dummy resistor capable of being coupled with the at least one magnetic storage cell at least for a write operation of the at least one magnetic storage cell, the selection device being coupled between the magnetic element and the at least one dummy resistor.

2. The magnetic memory of claim 1 wherein the selection device is a transistor having a source side.

3. The magnetic memory of claim 2 wherein the at least one dummy resistor is coupled to the source side of the selection device for at least one of the first write current and the second write current.

4. The magnetic memory of claim 1 wherein magnetic element has a first resistance and a second resistance higher than the first resistance, and wherein each of the at least one dummy resistor has a third resistance of 0.5 to 1.5 of the first resistance.

5. The magnetic memory of claim 4 wherein the third resistance of 0.8 to 1.15 of the first resistance.

6. The magnetic memory of claim 1 wherein the at least one dummy resistor is configured to provide a particular ratio between the first current and the second current.

7. The magnetic memory of claim 6 wherein the particular ratio is substantially one.

8. The magnetic memory of claim 1 wherein the dummy resistor is configured to be selectively coupled to or decoupled from the at least one magnetic storage cell.

9. The magnetic memory of claim 8 wherein the wherein the at least one dummy resistor is configured to be coupled with the at least one magnetic storage cell during a write operation of the magnetic storage cell and decoupled from the at least one magnetic storage cell during a read operation of the magnetic storage cell.

10. A magnetic memory comprising:

a plurality of magnetic storage cells, each of the plurality of magnetic storage cells including a magnetic element and a selection device coupled with the magnetic element, the magnetic element being programmed by a first write current driven through the magnetic element in a first direction and a second write current driven through the magnetic element in a second direction;

at least one source line corresponding to the plurality of magnetic storage cells, each of the at least one source line being coupled to the selection device of a first portion of the plurality of magnetic storage cells;

at least one bit line corresponding to the plurality of magnetic storage cells, each of the at least one source line being coupled to the selection device of a first portion of the plurality of magnetic storage cells;

a plurality of dummy resistors configured to be selectively coupled with the plurality of magnetic storage cells through the at least one source line or the at least one bit line at least for a write operation of the at least one magnetic storage cell, the selection device being coupled between the magnetic element and the plurality of dummy resistors.

11. The magnetic memory of claim 10 further comprising:

Bypass circuitry coupled with the at least one source line or the at least one bit line, the bypass circuitry configured to bypass the plurality of dummy resistors.

12. The magnetic memory of claim 11 wherein the bypass circuitry is configured to bypass the plurality of dummy resistors during a read operation.

13. The magnetic memory of claim 10 wherein the selection device is a transistor having a source side.

14. The magnetic memory of claim 13 wherein the plurality of dummy resistors is configured to be coupled on the source side of the selection device for the plurality of magnetic storage cells at least during the write operation of the at least one magnetic storage cell.

15. The magnetic memory of claim 13 wherein the plurality of dummy resistors is configured to be selectively coupled to or decoupled form the source side of the selection device for the plurality of magnetic storage cells.

16. The magnetic memory of claim 10 wherein magnetic element has a first resistance and a second resistance higher than the first resistance, and wherein each of the plurality of dummy resistors has a third resistance of 0.5 to 1.5 of the first resistance.

17. The magnetic memory of claim 16 wherein the third resistance of 0.8 to 1.15 of the first resistance.

18. The magnetic memory of claim 10 wherein the at least one dummy resistor is configured to provide a particular ratio between the first current and the second current.

19. The magnetic memory of claim 18 wherein the particular ratio is substantially one.

20. A method for utilizing a magnetic memory including a plurality of magnetic storage cells, at least one source line corresponding to the plurality of magnetic storage cells, and at least one bit line corresponding to the plurality of magnetic storage cells, each of the plurality of magnetic storage cells including a magnetic element and a selection device coupled with the magnetic element, the magnetic element being programmed by a first write current driven through the magnetic element in a first direction and a second write current driven through the magnetic element in a second direction, each of the at least one source line being coupled to the selection device of a first portion of the plurality of magnetic storage cells, each of the at least one source line being coupled to the selection device of a first portion of the plurality of magnetic storage cells, the method comprising:

selectively coupling at least one dummy resistor with a portion of the plurality of magnetic storage cells through the at least one source line or the at least one bit line at least for a write operation, the selection device being coupled between the magnetic element and the at least one dummy resistor;

driving the first write current or the second write current through the portion of the plurality of magnetic storage cells.

21. The method of claim 20 wherein the selection device is a transistor having a source side and wherein the selectively coupling further includes selectively coupling or decoupling the at least one dummy resistor on the source side of the selection device.

22. The method of claim 20 further comprising:

ensuring that the at least one dummy resistor is electrically decoupled from another portion of the plurality of magnetic storage cells during reading of the another portion of the plurality of magnetic storage cells.

23. The method of claim 20 wherein magnetic element has a first resistance and a second resistance higher than the first resistance, and wherein each of the at least one dummy resistor has a third resistance of 0.5 to 1.5 of the first resistance.

24. The method of claim 23 wherein the third resistance of 0.8 to 1.15 of the first resistance.

25. The method of claim 20 wherein the at least one dummy resistor is configured to provide a particular ratio between the first current and the second current.

26. The method of claim 20 wherein the particular ratio is substantially one.

27. A method for providing a magnetic memory comprising:

providing at least one magnetic storage cell, each of the at least one magnetic storage cell including a magnetic element and a selection device coupled with the magnetic element, the magnetic element being programmed by a first write current driven through the magnetic element in a first direction and a second write current driven through the magnetic element in a second direction; and

providing at least one dummy resistor capable of being coupled with the at least one magnetic storage cell at least for a write operation of the at least one magnetic storage cell, the selection device being coupled between the magnetic element and the at least one dummy resistor.

28. The method of claim 27 wherein at least one magnetic storage cell providing further includes:

providing the selection device is a transistor having a source side.

29. The method of claim 28 wherein the at least one dummy resistor providing further includes:

providing the dummy resistor capable of being coupled on the source side of the selection device for the first write current and the second write current.

30. The method of claim 27 wherein magnetic element has a first resistance and a second resistance higher than the first resistance, and wherein each of the at least one dummy resistor has a third resistance of 0.5 to 1.5 of the first resistance.

31. The method of claim 30 wherein the third resistance of 0.8 to 1.15 of the first resistance.

32. The method of claim 27 wherein the at least one dummy resistor is configured to provide a particular ratio between the first current and the second current.

33. The method of claim 27 wherein the particular ratio is substantially one.

34. The method of claim 27 wherein the at least one dummy resistor providing further includes:

configuring the at least one dummy resistor to be selectively coupled with or decoupled from the at least one magnetic storage cell.

35. The method of claim 34 wherein the at least one dummy resistor configuring further includes:

configuring the at least one dummy resistor to be selectively coupled with or decoupled from the at least one magnetic storage cell during a write operation.

36. The method of claim 34 wherein the at least one dummy resistor configuring further includes:

configuring the at least one dummy resistor to be selectively coupled with the at least one magnetic storage cell during a write operation of the magnetic storage cell and decoupled from the at least one magnetic storage cell during a read operation of the magnetic storage cell.