Apparatus and method for sharing I/O endpoints within a load store fabric by encapsulation of domain information in transaction layer packets

• US 7,188,209 B2
• Filed: 04/19/2004
• Issued: 03/06/2007
• Est. Priority Date: 04/18/2003
• Status: Active Grant

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: NextIO Incorporated
• Inventors: Khan, Asif, Pagan, Annette, Utley, Robert Haskell, Pekkala, Richard E., Pettey, Christopher J.
• Primary Examiner(s): HUYNH, KIM T
• Application Number:
  US10/827,117
• Publication Number:
  US 20040260842A1
• Time in Patent Office: 1,051 Days
• Field of Search: 710/305, 710/313, 710/316, 710/317, 710/105, 710/33, 710/36, 709/216, 709/220, 709/230, 709/250, 709/226, 370/351, 370/357, 370/362, 370/386, 370/399, 714/4
• US Class Current: 710/317
• CPC Class Codes: G06F 13/4022 using switching circuits, e.g. switching matrix, connection or expansion network G06F13/4009 takes precedence
• CPC Class Codes: G06F 2213/0026 PCI express
• CPC Class Codes: G06F 2213/0058 Bus-related hardware virtualisation

Abstract

An apparatus having a first plurality of I/O ports, a second I/O port, and core logic. The first plurality of I/O ports is coupled to a plurality of operating system domains (OSDs) through a load-store fabric, each routing transactions between the plurality of OSDs and the switching apparatus. The second I/O port is coupled to a first shared input/output endpoint. The first shared input/output endpoint requests/completes the transactions for each of the plurality of OSDs. The core logic is coupled to the first plurality of I/O ports and the second I/O port. The core logic routes the transactions between the first plurality of I/O ports and the second I/O port. The core logic designates a corresponding one of the plurality of OSDs according to a variant of a protocol, where the protocol provides for routing of the transactions only for a single OSD.

Claims

1. A switching apparatus for sharing input/output endpoints, the switching apparatus comprising:

a first plurality of I/O ports, coupled to a plurality of operating system domains (OSDs) through a load-store fabric, each configured to route transactions between said plurality of OSDs and the switching apparatus;

a second I/O port, coupled to a first shared input/output endpoint, wherein said first shared input/output endpoint is configured to request/complete said transactions for each of said plurality of OSDs; and

core logic, coupled to said first plurality of I/O ports and said second I/O port, configured to route said transactions between said first plurality of I/O ports and said second I/O port, wherein said core logic designates a corresponding one of said plurality of OSDs according to a variant of a protocol, and wherein said variant comprises encapsulating an OS domain header within a transaction layer packet that otherwise comports with said protocol, and wherein said protocol provides for routing of said transactions only for a single OSD.

2. The switching apparatus as recited in claim 1, wherein said first plurality of I/O ports communicates with said plurality of OSDs according to said protocol.

3. The switching apparatus as recited in claim 1, wherein said protocol comprises PCI Express.

4. The switching apparatus as recited in claim 3, wherein said core logic isolates said transactions over a plurality of PCI Express bus hierarchies according to said each of said plurality of OSDs.

5. The switching apparatus as recited in claim 4, wherein a subset of said transactions are routed in accordance with addressing mechanisms for a particular one of said plurality of PCI Express bus hierarchies, said particular one of said plurality of PCI Express bus hierarchies corresponding to a particular one of said plurality of OSDs.

6. The switching apparatus as recited in claim 1, wherein said core logic is configured to associate each of said transactions with a corresponding one of said plurality of OSDs, said corresponding one of said plurality of OSDs corresponding to one or more root complexes.

7. The switching apparatus as recited in claim 6, wherein said transaction layer packet is routed between said second I/O port and said first shared input/output endpoint.

8. The switching apparatus as recited in claim 7, wherein said first shared I/O endpoint is configured to detect said OS domain header and to perform a specified operation according to said protocol exclusively for said one of said plurality of OSDs.

9. The switching apparatus as recited in claim 1, wherein said first shared input/output endpoint designates one of said transactions for a particular one of said plurality of OSDs by encapsulating an OS domain header within a transaction layer packet, and wherein said transaction layer packet is routed to said core logic via said second I/O port.

10. The switching apparatus as recited in claim 9, wherein said core logic is configured to detect and decapsulate said OS domain header from said transaction layer packet, and is configured to route said one of said transactions to said particular one of said plurality of OSDs according to said protocol.

11. A shared input/output (I/O) switching mechanism, comprising:

core logic, configured to enable operating system domains to share one or more I/O endpoints over a load-store fabric, said core logic comprising;

global routing logic, configured to route first transactions to/from said operating system domains, and for routing second transactions to/from said one or more I/O endpoints, wherein each of said second transactions designates an associated one of said operating system domains for which an operation specified by each of said first transactions be performed, and wherein said associated one of said operating system domains is designated according to a variant of a protocol, and wherein said variant comprises encapsulating an OS domain header within a transaction layer packet that otherwise comports with said protocol, and wherein said protocol provides exclusively for a single operating system domain within said load-store fabric.

12. The shared I/O switching mechanism as recited in claim 11, wherein said protocol comprises PCI Express, and wherein said first transactions comport with said protocol.

13. The shared I/O switching mechanism as recited in claim 12, wherein said core logic isolates said first and second transactions over a plurality of PCI Express bus hierarchies according to each of said operating system domains.

14. The shared I/O switching mechanism as recited in claim 13, wherein said first and second transactions are routed in accordance with addressing mechanisms for a particular one of said plurality of PCI Express bus hierarchies, said particular one of said plurality of PCI Express bus hierarchies corresponding to said associated one of said operating system domains.

15. The shared I/O switching mechanism as recited in claim 11, wherein said core logic associates each of said operating system domains with each of a corresponding root complex.

16. The shared I/O switching mechanism as recited in claim 11, wherein said transaction layer packet is routed between said the shared I/O switching mechanism and one of said one or more I/O endpoints.

17. The shared I/O switching mechanism as recited in claim 16, wherein said one of said one or more I/O endpoints is configured to detect said OS domain header and to perform said operation according to said protocol exclusively for said one of said operating system domains.

18. The shared I/O switching mechanism as recited in claim 11, wherein one of said one or more I/O endpoints designates one of said second transactions for a particular one of said operating system domains by encapsulating an OS domain header within a transaction layer packet, and wherein said transaction layer packet is routed to the shared I/O switching mechanism.

19. The shared I/O switching mechanism as recited in claim 18, wherein VMAC logic within the shared I/O switching mechanism is configured to detect and decapsulate said OS domain header from said transaction layer packet, and wherein said core logic routes a corresponding one of said first transactions to said particular one of said plurality of operating system domains according to said protocol.