Tamper resistant shadow memory

• US 7,188,282 B2
• Filed: 12/02/2003
• Issued: 03/06/2007
• Est. Priority Date: 12/02/2002
• Status: Active Grant

• Current Assignee: Memjet Technology Ltd. (Memjet Limited)
• Original Assignee: Silverbrook Research Pty Limited
• Inventors: Walmsley, Simon Robert
• Primary Examiner(s): Ton; David
• Application Number:
  US10/727,251
• Publication Number:
  US 20040227205A1
• Time in Patent Office: 1,190 Days
• Field of Search: 347/19, 713/500, 713/194, 713/162, 365/145, 726/36, 355/18, 705/51, 714/718
• US Class Current: 714/718
• CPC Class Codes: B41J 2/04505 aiming at correcting alignment
• CPC Class Codes: B41J 2/04508 aiming at correcting other parameters
• CPC Class Codes: B41J 2/0451 for detecting failure, e.g. clogging, malfunctioning actuator
• CPC Class Codes: B41J 2/04528 aiming at warming up the head
• CPC Class Codes: B41J 2/04541 Specific driving circuit
• CPC Class Codes: B41J 2/04543 Block driving
• CPC Class Codes: B41J 2/04563 detecting head temperature; Ink temperature
• CPC Class Codes: B41J 2/04573 Timing; Delays
• CPC Class Codes: B41J 2/04586 controlling heads of a type not covered by groups B41J2/04575 - B41J2/04585, or of an undefined type
• CPC Class Codes: B41J 2202/20 Modules
• CPC Class Codes: G06F 21/554 involving event detection and direct action
• CPC Class Codes: G06F 21/57 Certifying or maintaining trusted computer platforms, e.g. secure boots or power-downs, version controls, system software checks, secure updates or assessing vulnerabilities
• CPC Class Codes: G06F 21/575 Secure boot
• CPC Class Codes: G06F 21/64 Protecting data integrity, e.g. using checksums, certificates or signatures
• CPC Class Codes: G06F 21/71 to assure secure computing or processing of information
• CPC Class Codes: G06F 21/73 by creating or determining hardware identification, e.g. serial numbers
• CPC Class Codes: G06F 21/74 operating in dual or compartmented mode, i.e. at least one secure mode
• CPC Class Codes: G06F 21/78 to assure secure storage of data address-based protection against unauthorised use of memory G06F12/14; record carriers for use with machines and with at least a part designed to carry digital markings G06K19/00
• CPC Class Codes: H03K 5/1252 Suppression or limitation of noise or interference specially adapted for transmission systems H04B15/00, H04L25/08
• CPC Class Codes: H04N 1/405 Halftoning, i.e. converting the picture signal of a continuous-tone original into a corresponding signal showing only two levels
• CPC Class Codes: Y10S 707/99933 : Query processing, i.e. searching
• CPC Class Codes: Y10S 707/99939 : Privileged access
• CPC Class Codes: Y10T 29/49401 : Fluid pattern dispersing device making, e.g., ink jet

Abstract

An integrated circuit comprising a processor and memory, the memory storing a set of data representing program code and/or an operating value, wherein each bit of the data is stored as a bit/inverse-bit pair in corresponding pairs of physically adjacent bit cells in the memory.

Claims

1. An integrated circuit comprising a processor and memory, the memory storing a set of data representing program code and/or an operating value, wherein each bit of the data is stored as a bit/inverse-bit pair in corresponding pairs of physically adjacent bit cells in the memory.

2. An integrated circuit according to claim 1, further including a memory management unit configured to receive a request for the set of data and to test, during processing of the request, whether the respective pairs of physically adjacent bit-cells that correspond to the set of data contain bit/inverse-bit pairs, thereby to confirm the validity of the set of data as stored in the memory.

3. An integrated circuit according to claim 2, wherein the memory management unit is configured to store sets of data as sets of bit/inverse-bit pairs in the memory.

4. An integrated circuit according to claim 2, configured to implement a defensive action in the event the test fails.

5. An integrated circuit according to claim 4, wherein the defensive action includes resetting the integrated circuit.

6. An integrated circuit according to claim 4, wherein the defensive reaction includes returning second data other than that the subject of the test.

7. An integrated circuit according to claim 6, wherein the second data is a string of identical digits.

8. An integrated circuit according to claim 4, wherein the defensive reaction is different depending upon whether the set of data represents program code or an operating value.

9. An integrated circuit according to claim 8, wherein, in the event the test fails and the set of data is an operating value, the integrated circuit is configured to replace the failed value with a substitute value.

10. An integrated circuit according to claim 9, wherein the substitute value is selected to disrupt a program running on the integrated circuit.

11. An integrated circuit according to claim 8, wherein, in the event the test fails and the set of data is a program code, the integrated circuit is configured to replace the failed value with a substitute value.

12. An integrated circuit according to claim 11, wherein the substitute value is selected to disrupt a program running on the integrated circuit.

13. An integrated circuit according to claim 12, wherein the substitute causes at least some circuitry on the integrated circuit to reset.

14. An integrated circuit according to claim 2, wherein, in the event the test fails, the integrated circuit is permanently prevented from running software.

15. An integrated circuit according to claim 2, wherein, in the event the test fails, the integrated circuit is configured to delete from the memory some or all of the bit values associated with the set of data.

16. An integrated circuit according to claim 2, wherein, in the event the test fails, the integrated circuit is configured to delete some or all of the contents of the memory.

17. An integrated circuit according to claim 1, selectively operable in either of first and second modes, wherein:

in the first mode, the memory management unit is configured to receive and process a request for the set of data, and to test, during processing of the request, whether the respective pairs of physically adjacent bit-cells corresponding to the set of data contain bit/inverse-bit pairs, thereby to confirm the validity of the set of data as stored in the memory; and

in the second mode, the memory management unit is configured to receive and process a request for data stored in the memory, without testing whether pairs of physically adjacent bit-cells contain bit/inverse-bit pairs.

18. An integrated circuit according to claim 17, wherein:

in the first mode, the memory management unit is configured to store a set of data associated with a memory write request as a corresponding set of bit/inverse-bit pairs, each of the bit/inverse-bit pairs being physically adjacent each other; and

in the second mode, the memory management unit is configured to store a set of data associated with a memory write request as the set of data without corresponding inverse-bits.

19. An integrated circuit according to claim 17, configured to boot into the first mode by default.