Parallel concatenated turbo code modulation encoder

• US 7,188,301 B1
• Filed: 01/08/2003
• Issued: 03/06/2007
• Est. Priority Date: 05/31/2002
• Status: Expired due to Fees

• Current Assignee: Broadcom Corporation (Broadcom, Inc.)
• Original Assignee: Broadcom Corporation (Broadcom, Inc.)
• Inventors: Shen, Ba-Zhong, Tran, Hau Thien, Cameron, Kelly Brian
• Primary Examiner(s): Torres; Joseph D.
• Application Number:
  US10/338,571
• Time in Patent Office: 1,518 Days
• Field of Search: 714/795, 714/794
• US Class Current: 714/794
• CPC Class Codes: H03M 13/258 with turbo codes, e.g. Turbo Trellis Coded Modulation [TTCM]
• CPC Class Codes: H03M 13/27 using interleaving techniques
• CPC Class Codes: H03M 13/6362 by puncturing
• CPC Class Codes: H04L 1/0041 Arrangements at the transmitter end
• CPC Class Codes: H04L 1/005 Iterative decoding, including iteration between signal detection and decoding operation
• CPC Class Codes: H04L 1/006 Trellis-coded modulation
• CPC Class Codes: H04L 1/0066 Parallel concatenated codes
• CPC Class Codes: H04L 1/0068 by puncturing

Abstract

Parallel concatenated turbo trellis encoder structure. A dual path turbo trellis coded modulation encoder employs two interleavers and two constituent encoders and is also operable to encode symbols whose code rate may vary on a symbol by symbol basis. In addition, each of the interleavers of the parallel concatenated turbo trellis encoder structure may perform modified interleaving where input bits are treated differently depending on the order in which they are received. This interleaving may be differentiated on a bit level. In some embodiments, the implementation of the parallel concatenated turbo trellis encoder structure ensures that the output order of encoded symbols is the same as the order in which the input is received. This input may itself be in the form of bits and/or symbols. Alternatively, the parallel concatenated turbo trellis encoder structure may also support a scrambled ordering of the encoded output with respect to the input.

Claims

1. An apparatus, comprising:

a top interleaver operably coupled to interleave at least some input bits of a plurality of input bits;

a top constituent trellis encoder, communicatively coupled to the top interleaver and operable to receive interleaved bits there from, that is operable to encode at least some input bits of the plurality of input bits that have been interleaved by the top interleaver;

a bottom interleaver that is also operably coupled to interleave at least some input bits of the plurality of input bits;

a bottom constituent trellis encoder, communicatively coupled to the bottom interleaver and operable to receive interleaved bits there from, that is operable to encode at least some input bits of the plurality of input bits that have been interleaved by the bottom interleaver;

a multiplexor (MUX) that alternatively selects encoded bits that are output from the top constituent trellis encoder and the bottom constituent trellis encoder to produce multiplexed bits that are arranged in an order corresponding to the alternative selecting of encoded bits that are output from the top constituent trellis encoder and encoded bits that are output from the bottom constituent trellis encoder;

a puncturing functional block that punctures a first plurality of bits of the multiplexed bits to produce a first encoded symbol and punctures a second plurality of bits of the multiplexed bits to produce a second encoded symbol; and

a symbol mapper that maps the first encoded symbol according to a first rate control and the second encoded symbol according to a second rate control.

2. The apparatus of claim 1, further comprising a rate control sequencer that provides a rate control sequence having a plurality of rate controls arranged in a period such that the first rate control and the second rate control are within the plurality of rate controls;

and wherein;

each rate control of the plurality of rate controls has a modulation selected from a plurality of modulations;

each modulation of the plurality of modulations has a constellation, a mapping, and a bandwidth efficiency.

3. The apparatus of claim 2, wherein:

one modulation of the plurality of modulations includes at least one of 8 Phase Shift Keying (PSK) modulation, Quadrature Phase Shift Keying (QPSK) modulation, 16 Quadrature Amplitude Modulation (QAM), and 16 Amplitude Phase Shift Keying (APSK) modulation.

4. The apparatus of claim 2, wherein:

a first modulation of the plurality of modulations is a 16 Quadrature Amplitude Modulation (QAM); and

a second modulation of the plurality of modulations is a 16 Amplitude Phase Shift Keying (APSK) modulation.

5. The apparatus of claim 2, wherein:

one modulation of the plurality of modulations includes a Quadrature Phase Shift Keying (QPSK) modulation having constellation points that are titled with respect to axes of an I,Q (in-phase and quadrature) plane.

6. The apparatus of claim 2, wherein:

a first modulation of the plurality of modulations includes a Quadrature Phase Shift Keying (QPSK) modulation having constellation points located further from an origin of the I,Q (in-phase and quadrature) plane than constellation points of a second modulation of the plurality of modulations that also includes a Quadrature Phase Shift Keying (QPSK) modulation.

7. The apparatus of claim 1, wherein:

the apparatus generates output; and

the output includes the first encoded symbol and at least one uncoded bit.

8. The apparatus of claim 1, wherein:

the apparatus provides the first encoded symbol on an Additive White Gaussian Noise (AWGN) communication channel.

9. The apparatus of claim 1, wherein:

the plurality of input bits are provided serially to the apparatus;

a predetermined number of input bits of the plurality of input bits are grouped to form an input symbol.

10. The apparatus of claim 1, wherein:

the plurality of input bits are provided serially to the apparatus; and

two consecutive input bits of the plurality of input bits, that are provided serially to the apparatus, form an input symbol.

11. The apparatus of claim 1, wherein:

the plurality of input bits includes a plurality of input symbols;

two consecutive input bits of the plurality of input bits form an input symbol of the plurality of input symbols;

the top constituent trellis encoder and the bottom constituent trellis encoder encode the plurality of input symbols using an 8 state trellis to produce a plurality of encoded symbols; and

the apparatus is a rate 2/5 non-systematic encoder.

12. The apparatus of claim 11, wherein:

the plurality of encoded symbols are arranged in a frame; and

each encoded symbol of the plurality of encoded symbols corresponds to a trellis stage of the 8 state trellis.

13. The apparatus of claim 1, wherein:

the puncturing functional block punctures a first plurality of bits of the multiplexed bits to produce the first encoded symbol and a third encoded symbol.

14. The apparatus of claim 1, wherein:

the top interleaver performs modified interleaving of the plurality of input bits; and

the modified interleaving includes interleaving only odd positioned bits of the plurality of input bits.

15. The apparatus of claim 1, wherein:

the bottom interleaver performs modified interleaving of the plurality of input bits; and

the modified interleaving includes interleaving only even positioned bits of the plurality of input bits.

16. The apparatus of claim 1, wherein:

the plurality of input bits are provided to the apparatus according to an order;

the apparatus generates a plurality of encoded symbols; and

the plurality of encoded symbols are output from the apparatus according to the order in which the plurality of input bits are provided to the apparatus.

17. The apparatus of claim 1, wherein:

the apparatus is a systematic encoder.

18. The apparatus of claim 1, wherein:

the apparatus is a non-systematic encoder.

19. The apparatus of claim 1, wherein:

the apparatus is an encoder that is contained within a satellite transmitter;

the satellite transmitter is communicatively coupled to a satellite receiver via a wireless communication channel; and

the satellite receiver is a decoder that is operable to decode the first encoded symbol.

20. The apparatus of claim 1, wherein:

the apparatus is an encoder is that contained within a satellite communication system, a high definition television (HDTV) communication system, a cellular communication system, a microwave communication system, a point-to-point radio communication system, or a turbo trellis coded modulation (TTCM) communication system.

21. An apparatus, comprising:

a rate control sequencer that provides a rate control sequence having a plurality of rate controls arranged in a period, wherein;

each rate control of the plurality of rate controls has a modulation selected from a plurality of modulations;

each modulation of the plurality of modulations has a constellation, a mapping, and a bandwidth efficiency;

a top interleaver operably coupled to interleave at least some input bits of a plurality of input bits;

a top constituent trellis encoder, communicatively coupled to the top interleaver and operable to receive interleaved bits there from, that is operable to encode at least some input bits of the plurality of input bits that have been interleaved by the top interleaver;

a bottom interleaver that is also operably coupled to interleave at least some input bits of the plurality of input bits;

a bottom constituent trellis encoder, communicatively coupled to the bottom interleaver and operable to receive interleaved bits there from, that is operable to encode at least some input bits of the plurality of input bits that have been interleaved by the bottom interleaver;

a multiplexor (MUX) that alternatively selects encoded bits that are output from the top constituent trellis encoder and the bottom constituent trellis encoder to produce multiplexed bits that are arranged in an order corresponding to the alternative selecting of encoded bits that are output from the top constituent trellis encoder and encoded bits that are output from the bottom constituent trellis encoder;

a puncturing functional block that punctures a first plurality of bits of the multiplexed bits according to a first rate control of the plurality of rate controls to produce a first encoded symbol and punctures a second plurality of bits of the multiplexed bits according to a second rate control of the plurality of rate controls to produce a second encoded symbol; and

a symbol mapper that maps the first encoded symbol according to the first rate control and the second encoded symbol according to the second rate control.

22. The apparatus of claim 21, wherein:

the apparatus provides the first encoded symbol on an Additive White Gaussian Noise (AWGN) communication channel.

23. The apparatus of claim 21, wherein:

the plurality of input bits includes a plurality of input symbols;

two consecutive input bits of the plurality of input bits form an input symbol of the plurality of input symbols;

the top constituent trellis encoder and the bottom constituent trellis encoder encode the plurality of input symbols using an 8 state trellis to produce a plurality of encoded symbols;

the apparatus is a rate 2/5 non-systematic encoder;

the plurality of encoded symbols are arranged in a frame; and

each encoded symbol of the plurality of encoded symbols corresponds to a trellis stage of the 8 state trellis.

24. The apparatus of claim 21, wherein:

one modulation of the plurality of modulations includes at least one of 8 Phase Shift Keying (PSK) modulation, Quadrature Phase Shift Keying (QPSK) modulation, 16 Quadrature Amplitude Modulation (QAM), and 16 Amplitude Phase Shift Keying (APSK) modulation.

25. The apparatus of claim 21, wherein:

one modulation of the plurality of modulations includes a Quadrature Phase Shift Keying (QPSK) modulation having constellation points that are titled with respect to axes of an I,Q (in-phase and quadrature) plane.

26. The apparatus of claim 21, wherein:

a first modulation of the plurality of modulations includes a Quadrature Phase Shift Keying (QPSK) modulation having constellation points located further from an origin of the I,Q (in-phase and quadrature) plane than constellation points of a second modulation of the plurality of modulations that also includes a Quadrature Phase Shift Keying (QPSK) modulation.

27. The apparatus of claim 21, wherein:

the top interleaver performs first modified interleaving of the plurality of input bits;

the first modified interleaving includes interleaving only odd positioned bits of the plurality of input bits;

the bottom interleaver performs second modified interleaving of the plurality of input bits; and

the second modified interleaving includes interleaving only even positioned bits of the plurality of input bits.

28. The apparatus of claim 21, wherein:

the plurality of input bits are provided to the apparatus according to an order;

the apparatus generates a plurality of encoded symbols; and

the plurality of encoded symbols are output from the apparatus according to the order in which the plurality of input bits are provided to the apparatus.

29. The apparatus of claim 21, wherein:

the apparatus is a systematic encoder or a non-systematic encoder.

30. The apparatus of claim 21, wherein:

the apparatus is an encoder that is contained within a satellite communication system, a high definition television (HDTV) communication system, a cellular communication system, a microwave communication system, a point-to-point radio communication system, or a turbo trellis coded modulation (TTCM) communication system.

31. An apparatus comprising:

a rate control sequencer that provides a rate control sequence having a plurality of rate controls arranged in a period, wherein;

each rate control of the plurality of rate controls has a modulation selected from a plurality of modulations;

each modulation of the plurality of modulations has a constellation, a mapping, and a bandwidth efficiency;

a top interleaver operably coupled to interleave at least some input bits of the plurality of input bits;

a top constituent trellis encoder, communicatively coupled to the top interleaver and operable to receive interleaved bits there from, that is operable to encode at least some input bits of the plurality of input bits that have been interleaved by the top interleaver;

a bottom interleaver that is also operably coupled to interleave at least some input bits of the plurality of input bits;

a bottom constituent trellis encoder, communicatively coupled to the bottom interleaver and operable to receive interleaved bits there from, that is operable to encode at least some input bits of the plurality of input bits that have been interleaved by the bottom interleaver;

a multiplexor (MUX) that alternatively selects encoded bits that are output from the top constituent trellis encoder and the bottom constituent trellis encoder to produce multiplexed bits that are arranged in an order corresponding to the alternative selecting of encoded bits that are output from the top constituent trellis encoder and encoded bits that are output from the bottom constituent trellis encoder;

a puncturing functional block that punctures a first plurality of bits of the multiplexed bits according to a first rate control of the plurality of rate controls to produce a first encoded symbol and punctures a second plurality of bits of the multiplexed bits according to a second rate control of the plurality of rate controls to produce a second encoded symbol; and

a symbol mapper that maps the first encoded symbol according to the first rate control and the second encoded symbol according to the second rate control; and

wherein;

the top interleaver performs modified interleaving of the plurality of input bits;

the modified interleaving includes interleaving only odd positioned bits of the plurality of input bits;

the bottom interleaver performs modified interleaving of the plurality of input bits; and

the modified interleaving includes interleaving only even positioned bits of the plurality of input bits.

32. The apparatus of claim 31, wherein:

the apparatus generates output; and

the output includes the first encoded symbol and at least one uncoded bit.

33. The apparatus of claim 31, wherein:

the apparatus provides the first encoded symbol on an Additive White Gaussian Noise (AWGN) communication channel.

34. The apparatus of claim 31, wherein:

the plurality of input bits includes a plurality of input symbols;

two consecutive input bits of the plurality of input bits form an input symbol of the plurality of input symbols;

the top constituent trellis encoder and the bottom constituent trellis encoder encode the plurality of input symbols using an 8 state trellis to produce a plurality of encoded symbols;

the apparatus is a rate 2/5 non-systematic encoder;

the plurality of encoded symbols are arranged in a frame; and

each encoded symbol of the plurality of encoded symbols corresponds to a trellis stage of the 8 state trellis.

35. The apparatus of claim 31, wherein:

one modulation of the plurality of modulations includes at least one of 8 Phase Shift Keying (PSK) modulation, Quadrature Phase Shift Keying (QPSK) modulation, 16 Quadrature Amplitude Modulation (QAM), and 16 Amplitude Phase Shift Keying (APSK) modulation.

36. The apparatus of claim 31, wherein:

a first modulation of the plurality of modulations is a 16 Quadrature Amplitude Modulation (QAM); and

a second modulation of the plurality of modulations is a 16 Amplitude Phase Shift Keying (APSK) modulation.

37. The apparatus of claim 31, wherein:

one modulation of the plurality of modulations includes a Quadrature Phase Shift Keying (QPSK) modulation having constellation points that are titled with respect to axes of an I,Q (in-phase and quadrature) plane.

38. The apparatus of claim 31, wherein:

a first modulation of the plurality of modulations includes a Quadrature Phase Shift Keying (QPSK) modulation having constellation points located further from an origin of the I,Q (in-phase and quadrature) plane than constellation points of a second modulation of the plurality of modulations that also includes a Quadrature Phase Shift Keying (QPSK) modulation.

39. The apparatus of claim 31, wherein:

the apparatus is a systematic encoder or a non-systematic encoder.

40. The apparatus of claim 31, wherein:

the apparatus is an encoder that is contained within a satellite communication system, a high definition television (HDTV) communication system, a cellular communication system, a microwave communication system, a point-to-point radio communication system, or a turbo trellis coded modulation (TTCM) communication system.