Thin film transistor array panel for a liquid crystal display

• US 7,189,998 B2
• Filed: 04/29/2002
• Issued: 03/13/2007
• Est. Priority Date: 10/29/1998
• Status: Expired due to Term

• Current Assignee: Samsung Display Company Limited (Samsung Electronics Co. Ltd.)
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Cha, Jong-Hwan, Yi, Dae-Sung, Jang, Geun-Ha
• Primary Examiner(s): Flynn; Nathan J.
• Assistant Examiner(s): SEFER, AHMED N
• Application Number:
  US10/133,340
• Publication Number:
  US 20020115298A1
• Time in Patent Office: 1,779 Days
• Field of Search: 257/72, 257/59, 349/42
• US Class Current: 257/72
• CPC Class Codes: H01L 27/12 the substrate being other than a semiconductor body, e.g. an insulating body
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 27/1288 employing particular masking sequences or specially adapted masks, e.g. half-tone mask

Abstract

A gate insulating layer, an amorphous silicon layer, a doped amorphous silicon layer and a Cr layer are sequentially deposited on a substrate on which a gate wire is formed. Next, the Cr layer is patterned to form a data line, a source electrode and a drain electrode. The doped amorphous silicon layer and the amorphous silicon layer are patterned at the same time, and the doped amorphous silicon layer is etched by using the data line, the source electrode and the drain electrode as etch stopper. Subsequently, a passivation layer is deposited and patterned to form a contact hole. An ITO layer is deposited and patterned to form a pixel electrode. According to the present invention, an oxide layer is prevented by performing a sequential deposition of the four layers in a vacuum state. As a result, the on current of the TFT is increased, and HF cleaning is not necessary because no oxide layer is formed. Therefore, the overall TFT manufacturing process is simplified.

Claims

1. A thin film transistor array panel, comprising:

an insulating substrate;

a gate wire including a gate line formed on the insulating substrate and a gate electrode connected to the gate line;

a gate insulating layer formed on the gate wire;

a data line formed on the gate insulating layer and crossing the gate line, the data line comprising an amorphous silicon layer, a doped amorphous silicon layer and a metal layer;

a channel portion formed of the amorphous silicon layer on the gate insulating layer over the gate electrode;

a source electrode connected to the data line, wherein at least a portion of the source electrode is formed on the channel portion;

a drain electrode formed on the channel portion and spaced apart from the source electrode;

a passivation layer covering the data line, the channel portion and the gate insulating layer, and having a contact hole exposing at least a portion of the drain electrode; and

a pixel electrode formed on the passivation layer and connected to the drain electrode through the contact hole,

wherein the amorphous silicon layer of the data line has a portion narrower than the metal layer of the data line, and wherein the passivation layer covering the data line has a groove formed under the metal layer of the data line.

2. The thin film transistor array panel of claim 1, wherein the source electrode and the drain electrode comprise the doped amorphous layer and the metal layer.

3. The thin film transistor array panel of claim 1, wherein the gate wire has a double layered structure comprising a first metal layer formed of Al or Al—

Nd and a second metal layer formed of Mo, Ta, Cr or alloys thereof.

4. The thin film transistor array panel of claim 3, wherein the metal layer of the data line is formed of Cr.

5. The thin film transistor array panel of claim 1, wherein the pixel electrode is formed on indium tin oxide (ITO).

6. The thin film transistor array panel of claim 1, wherein the groove formed under the metal layer of the data line is a thinned portion of the passivation layer adjacent to at least one of the amorphous silicon layer and the doped amorphous silicon layer of the data line.