Selecting die placement on a semiconductor wafer to reduce test time

• US 7,190,183 B1
• Filed: 03/12/2004
• Issued: 03/13/2007
• Est. Priority Date: 03/12/2003
• Status: Active Grant

• Current Assignee: PDF Solutions
• Original Assignee: PDF Solutions
• Inventors: Cadouri, Eitan
• Primary Examiner(s): HOLLINGTON, JERMELE M
• Application Number:
  US10/799,061
• Time in Patent Office: 1,096 Days
• Field of Search: 324/537, 324/754, 324/756, 438/5, 438/8, 438/15, 438 17- 18, 438/107, 297/12, 297/20, 29832-833, 716/2, 716/4, 716/8
• US Class Current: 324/750.01
• CPC Class Codes: G01R 31/31718 Logistic aspects, e.g. binning, selection, sorting of devices under test, tester/handler interaction networks, Test management software, e.g. software for test statistics or test evaluation, yield analysis mechanical aspects G01R31/2808, G01R31/2851

Abstract

A die placement of dies on a wafer is selected to reduce test time of the dies by obtaining a die placement and determining placements of a tester head needed to test the dies in the die placement. A number of touchdowns needed in the determined placements of the tester head is determined, where a touchdown involves lowering the tester head to form an electrical contact between pins on the tester head and bonding pads on a die being tested. The die placement is adjusted to reduce the number of touchdowns.

Claims

1. A method of selecting a die placement of dies on a wafer to reduce test time of the dies, the method comprising:

a) obtaining a die placement of dies on the wafer, wherein the die placement defines the locations on the wafer on which the dies are to be fabricated;

b) determining placements of a tester head needed to test the dies in the die placement;

c) determining a number of touchdowns needed in the determined placements of the tester head, wherein a touchdown involves lowering the tester head to form an electrical contact between pins on the tester head and bonding pads on a die being tested; and

d) adjusting the die placement to reduce the number of touchdowns.

2. The method of claim 1 wherein steps b) to d) are iterated to obtain a die placement with a minimum number of touchdowns needed to test the dies in the die placement.

3. The method of claim 1, wherein the placements of the tester head are determined based on a test program.

4. The method of claim 3, wherein steps a) to d) are iterated for different test programs to determine a combination of die placement and test program with a minimum number of touchdowns.

5. The method of claim 4, wherein steps a) to d) are iterated for different tester heads to determine a combination of die placement test program, and tester head with a minimum number of touchdowns.

6. The method of claim 1, wherein steps a) to d) are iterated for different tester heads to determine a combination of die placement and tester head with a minimum number of touchdowns.

7. The method of claim 1, wherein the taster head is configured to simultaneously test a set of multiple dies.

8. A method of selecting a die placement of dies on a wafer to reduce test time of the dies, the method comprising:

a) obtaining a die placement of dies on the wafer, wherein the die placement defines the locations on the wafer on which the dies are to be fabricated;

b) obtaining a configuration of a tester head used to test the dies on the wafer;

c) determining placements of the tester head needed to test the dies in the die placement using the configuration of the tester head;

d) determining a number of touchdowns needed in the determined placements of the tester head; and

e) adjusting the die placement to reduce the number of touchdowns.

9. The method of claim 8, wherein steps c) to e) are iterated to obtain a die placement with a minimum number of touchdowns needed to test the dies in the die placement.

10. The method of claim 8, wherein the placements of the tester head are determined based on a test program.

11. The method of claim 10, wherein steps a) to e) are iterated for different test programs of tester heads to determine a combination of die placement and test program with a minimum number of touchdowns.

12. The method of claim 11, wherein steps a) to e) are iterated for different configurations of tester heads to determine a combination of die placement, test program, and configuration of tester head with a minimum number of touchdowns.

13. The method of claim 8, wherein steps a) to e) are iterated for different configuration of tester heads to determine a combination of die placement and configuration of tester head with a minimum number of touchdowns.

14. A system of selecting a die placement of dies on a wafer to reduce test time of the dies, the system comprising:

an initial die placement of dies on the wafer, wherein the initial die placement defines the locations on the wafer on which the dies are to be fabricated;

a tester head having pins to contact bonding pads on a die on the wafer being tested; and

an adjusted die placement, wherein the adjusted die placement is derived from the initial die placement by determining placements of the tester head needed to test the dies on the initial die placement and a number of touchdowns needed in the determined placements of the tester head, and wherein the adjusted die placement requires fewer touchdowns by the test head to test the dies on the adjusted die placement than the dies on the initial die placement.

15. The system of claim 14, wherein the initial die placement and the adjusted die placement have the sane number of dies.

16. The system of claim 14, wherein the tester head is configured to simultaneously test a set of multiples dies.