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Integrated circuit incorporating three-dimensional memory array with dual opposing decoder arrangement

  • US 7,190,602 B2
  • Filed: 02/09/2004
  • Issued: 03/13/2007
  • Est. Priority Date: 11/16/1998
  • Status: Expired due to Term
First Claim
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1. An integrated circuit having two respective decode/selection circuits respectively located along opposite edges of a three-dimensional memory array for selecting wordlines which respectively exit the memory array along said opposite edges or for selecting bitlines which respectively exit the memory array along said opposite edges.

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